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1 preliminary data sheet, rev. 1.0 91-sr-011-05-8l mobile diskonchip g3 512mbit/1gbit flash disk with mlc nand and m-systems? x2 technology preliminary data sheet, june 2003 highlights mobile diskonchip g3 is one of the industry?s most efficient storage solutions, using toshiba?s 0.13 m multi-level cell (mlc) nand flash technology and x2 technology from m-systems?. mlc nand flash technology provides the smallest die size by storing 2 bits of information in a single memory cell. x2 technology enables mlc nand to achieve highly reliable, high-performance data and code storage with a specially designed error detection and correction mechanism, optimized file management, and proprietary algorithms for enhanced performance. further cost benefits derive from the cost-effective architecture of mobile diskonchip g3, which includes a boot block that can replace expensive nor flash, and incorporates both the flash array and an embedded thin controller in a single die. mobile diskonchip g3 provides: flash disk for both code and data storage low voltage: 1.8v or 3.3 i/o (auto-detect), 3v core hardware protection and security-enabling features high capacity: single die - 512mb (64mb), dual die - 1gb (128mb) device cascade capacity: up to 2gb (256mb) enhanced programmable boot block enabling execute in place (xip) functionality using 16-bit interface small form factors: 512mb (64mb) capacity (single die): 48-pin tsop-i package 85-ball fbga 7x10 mm package 1gb (128mb) capacity (dual die): 69-ball fbga 9x12 mm package enhanced performance by implementation of: multi-plane operation dma support multiburst operation turbo operation unrivaled data integrity with a robust error detection code/erro r correction code (edc/ecc) tailored for mlc nand flash technology maximized flash endurance with trueffs ? 6.1 (and higher) support for major mobile operating systems (oss), including symbian os, pocket pc 2002/3, smartphone 2002/3, palm os, nucleus, linux, windows ce, and more. compatible with major mobile cpus, including ti omap, xscale, motorola dragonball mx1 and qualcomm msmxxxx.
mobile diskonchip g3 2 data sheet, rev. 1.0 91-sr-011-05-8l performance multiburst read: 80 mb/sec erase: 30 mb/sec sustained read: 5 mb/sec sustained write: 1.1 mb/sec access time: normal: 55 nsec turbo: 33 nsec multiburst: 25 nsec protection & security-enabling features 16-byte unique identification (uid) number 6kbyte user-controlled one time programmable (otp) area two configurable hardware-protected partitions for data and code: read-only mode write-only mode one-time write mode (rom-like) partition protection key and lock# signal sticky lock (slock) to lock boot partition protected bad block table reliability and data integrity hardware- and software-driven, on-the-fly edc and ecc algorithms 4-bit error detection code/error correction code (edc/ecc), based on a patented combination of bch and hamming code algorithms, tailored for mlc nand flash technology guaranteed data integrity after power failure transparent bad-block management dynamic and static wear-leveling boot capability programmable boot block with xip capability to replace boot nor 2kb for 512mb devices 4kb for 1gb devices download engine (de) for automatic download of boot code from programmable boot block boot options: cpu initialization platform initialization os boot asynchronous boot mode to boot from arm-based cpus, e.g. xscale, ti omap, without the need for external glue logic exceptional boot performance with multiburst operation and dma support enhanced by external clock hardware compatibility configurable interface: simple nor-like or multiplexed address/data interface cpu compatibility, including: arm-based cpus texas instruments omap intel strongarm/xscale motorola dragonball mx1 qualcomm msmxxxx amd alchemy motorola powerpc? mpc8xx philips pr31700 hitachi superh? sh-x nec vr series supports 8-, 16- and 32-bit architectures
mobile diskonchip g3 3 data sheet, rev. 1.0 91-sr-011-05-8l trueffs ? software full hard-disk read/write emulation for transparent file system management patented trueffs flash file system management automatic block management data management to maximize the limit of typical flash life expectancy dynamic virtual mapping dynamic and static wear-leveling programming, duplica ting, testing and debugging tools available in source code operating environment wide os support, including: symbian os (epoc) pocket pc 2002/3 smartphone 2002/3 palm os nucleus windows ce linux trueffs software development kit (sdk) for quick and easy support for proprietary oss, or os-less environment trueffs boot software development kit (bdk) power requirements operating voltage core: 2.5v to 3.6v i/o: 1.65 to 2.0v; or 2.5v to 3.6v (auto-detect) current active: 10 ma deep power-down: 10 a (512mb) 20 a (1gb) capacity and packaging 512mb (64mb) capacity (single die): device cascading option for up to four devices (2gb) 48-pin tsop-i package: 20x12x1.2 mm (width x length x height) 85-ball fbga package: 7x10x1.2 mm (width x length x height) pinout compatible with diskonchip plus tsop-i products ballout compatible with diskonchip plus fbga products: 9x12 mm 1gb (128mb) capacity (dual die): device cascading option for up to two devices (2gb) 69-ball fbga package: 9x12x1.4 mm (width x length x height) ballout compatible with mobile diskonchip g3 512mb and diskonchip plus fbga products: 9x12 mm
mobile diskonchip g3 1 data sheet, rev. 1.0 91-sr-011-05-8l t able of c ontents 1. introduction ................................................................................................................... ............ 5 2. product overview ............................................................................................................... ....... 6 2.1 product description ............................................................................................................ 6 2.2 512mb standard interface .................................................................................................. 7 2.2.1 pin/ball di agrams .............................................................................................................. ... 7 2.2.2 system in terface ............................................................................................................... ... 9 2.2.3 signal desc riptio n ............................................................................................................. .10 2.3 1gb standard interface .................................................................................................... 14 2.3.1 ball diag ram ................................................................................................................... .... 14 2.3.2 system in terface ............................................................................................................... .15 2.3.3 signal desc riptio n ............................................................................................................. .16 2.4 512mb multiplexed interface ............................................................................................ 18 2.4.1 pin/ball diagram............................................................................................................... .. 18 2.4.2 system in terface ............................................................................................................... .20 2.4.3 signal desc riptio n ............................................................................................................. .21 2.5 1gb multiplexed interface................................................................................................. 25 2.5.1 ball diag ram ................................................................................................................... .... 25 2.5.2 system in terface ............................................................................................................... .26 2.5.3 signal desc riptio n ............................................................................................................. .27 3. theory of operation ............................................................................................................ .... 29 3.1 overview....................................................................................................................... .... 29 3.2 system interface............................................................................................................... 30 3.2.1 standard (nor-like) interface........................................................................................... 30 3.2.2 multiplexed interface .......................................................................................................... 30 3.3 configuration interface ..................................................................................................... 31 3.4 protection and security-enabling features ...................................................................... 31 3.4.1 read/write pr otection ........................................................................................................ 31 3.4.2 unique identificati on (uid) nu mber ................................................................................... 31 3.4.3 one-time programm able (otp) area ............................................................................... 32 3.4.4 one-time write (rom-l ike) part ition ................................................................................ 32 3.4.5 sticky lock (slock ).......................................................................................................... 32 3.5 programmable boot block with execute in place (xip) functionality.............................. 32 3.6 download engine (de) ..................................................................................................... 33 3.7 error detection code/error correction code (edc/ecc) ................................................ 33
mobile diskonchip g3 2 data sheet, rev. 1.0 91-sr-011-05-8l 3.8 data pipeline .................................................................................................................. .. 33 3.9 control and status............................................................................................................ 3 3 3.10 flash architecture............................................................................................................. 34 4. x2 technology .................................................................................................................. ....... 36 4.1 multiburst operation......................................................................................................... 36 4.2 dma operation................................................................................................................. 3 8 4.3 combined multiburst mode and dma operation ............................................................. 39 4.4 turbo operation ............................................................................................................... 3 9 5. hardware protection ............................................................................................................ ... 40 5.1 method of operation......................................................................................................... 40 5.2 low-level structure of the protected area....................................................................... 41 6. modes of operation............................................................................................................. .... 43 6.1 normal mode .................................................................................................................... 44 6.2 reset mode ..................................................................................................................... .44 6.3 deep power-down mode ................................................................................................. 44 7. trueffs technology............................................................................................................. .. 46 7.1 general description.......................................................................................................... 46 7.1.1 built-in operating system s upport..................................................................................... 47 7.1.2 trueffs software develo pment kit (sdk)........................................................................ 47 7.1.3 file mana gement................................................................................................................ 47 7.1.4 bad block m anagement ..................................................................................................... 47 7.1.5 wear-leveling .................................................................................................................. .. 47 7.1.6 power failure management ............................................................................................... 48 7.1.7 error detection/ correction.................................................................................................. 48 7.1.8 special features through i/o control (ioctl ) mechani sm.............................................. 49 7.1.9 compatib ility .................................................................................................................. ..... 49 7.2 8kb memory window ....................................................................................................... 49 8. register descriptions .......................................................................................................... ... 50 8.1 definition of terms ........................................................................................................... 5 0 8.2 reset values ................................................................................................................... .50 8.3 no operation (nop) register........................................................................................... 51 8.4 chip identification (id) register [0:1]................................................................................ 51 8.5 test register .................................................................................................................. .. 51 8.6 bus lock register ............................................................................................................ 52 8.7 endian control register ................................................................................................... 53
mobile diskonchip g3 3 data sheet, rev. 1.0 91-sr-011-05-8l 8.8 diskonchip control register/control confirmation register ........................................... 54 8.9 device id select register................................................................................................. 55 8.10 configuration register...................................................................................................... 55 8.11 interrupt control register ................................................................................................. 56 8.12 interrupt status register................................................................................................... 57 8.13 output control register.................................................................................................... 58 8.14 dpd control register ....................................................................................................... 59 8.15 dma control register [1:0]............................................................................................... 60 8.16 multiburst mode control register..................................................................................... 62 9. booting from mobile diskonchip g3 .................................................................................... 63 9.1 introduction................................................................................................................... .... 63 9.2 boot procedure in pc-compatible platforms ................................................................... 63 9.3 boot replacement ............................................................................................................ 64 9.3.1 pc archit ectures ............................................................................................................... .64 9.3.2 non-pc archit ecture s......................................................................................................... 65 9.3.3 asynchronous b oot mode .................................................................................................. 65 10. design considerations .......................................................................................................... .66 10.1 general guidelines........................................................................................................... 66 10.2 standard nor-like interface ........................................................................................... 67 10.3 multiplexed interface ........................................................................................................ 68 10.4 connecting control signals .............................................................................................. 68 10.4.1 standard inte rface............................................................................................................. .68 10.4.2 multiplexed interface .......................................................................................................... 69 10.5 implementing the interrupt mechanism ............................................................................ 70 10.5.1 hardware conf iguratio n ..................................................................................................... 70 10.5.2 software confi guratio n....................................................................................................... 70 10.6 device cascading............................................................................................................. 71 10.7 boot replacement ............................................................................................................ 72 10.8 platform-specific issues ................................................................................................... 73 10.8.1 wait state ..................................................................................................................... ...... 73 10.8.2 big and little endi an systems............................................................................................ 73 10.8.3 busy signal.................................................................................................................... ..... 73 10.8.4 working with 8/16/ 32-bit systems...................................................................................... 73 10.9 design environment ......................................................................................................... 75
mobile diskonchip g3 4 data sheet, rev. 1.0 91-sr-011-05-8l 11. product specifications ......................................................................................................... .. 76 11.1 environmental specifications ........................................................................................... 76 11.1.1 operating tem peratur e ...................................................................................................... 76 11.1.2 thermal charac teristics ..................................................................................................... 76 11.1.3 humidity....................................................................................................................... ....... 76 11.1.4 enduran ce ...................................................................................................................... .... 76 11.2 electrical specifications.................................................................................................... 76 11.2.1 absolute maximu m ratings................................................................................................ 76 11.2.2 capacitance.................................................................................................................... .... 77 11.2.3 dc electrical characteristic s over operat ing rang e ........................................................ 77 11.2.4 ac operating conditions.................................................................................................... 79 11.3 timing specifications........................................................................................................ 80 11.3.1 read cycle timing st andard inte rface .............................................................................. 80 11.3.2 write cycle timing st andard inte rface .............................................................................. 82 11.3.3 read cycle timing mult iplexed inte rface........................................................................... 83 11.3.4 write cycle timing mult iplexed inte rface........................................................................... 84 11.3.5 read cycle timi ng multiburst ............................................................................................ 85 11.3.6 power supply sequence .................................................................................................... 86 11.3.7 power-up timing ................................................................................................................ 86 11.3.8 interrupt timing ............................................................................................................... ... 88 11.3.9 dma request timing ......................................................................................................... 88 11.4 mechanical dimensions.................................................................................................... 89 11.4.1 mobile diskonchip g3 512mb........................................................................................... 89 11.4.2 mobile diskonchip g3 1gb (dual-die) ............................................................................. 91 12. ordering information........................................................................................................... .... 92 how to contact us .............................................................................................................. .......... 93
mobile diskonchip g3 5 data sheet, rev. 1.0 91-sr-011-05-8l 1. i ntroduction this data sheet includes the following sections: section 1: overview of data sheet contents section 2: product overview, including a brief product description, ball diagrams and signal descriptions section 3: theory of operation for the major building blocks section 4: major features and benefits of x2 technology section 5: detailed description of hardware pr otection and security-enabling features section 6: modes of operation section 7: trueffs technology, including power failu re management and 8kbyte memory window section 8: register descriptions section 9: booting from mobile diskonchip g3 section 10: hardware and software design considerations section 11: environmental, electrical, tim ing and product specifications section 12: information on ordering mobile diskonchip g3 for additional information on the product name of m-systems? flash disk products, please contact one of the offices listed on the back page.
mobile diskonchip g3 6 data sheet, rev. 1.0 91-sr-011-05-8l 2. p roduct o verview 2.1 product description mobile diskonchip g3 is the latest addition to m-systems? diskonchip product family. mobile diskonchip g3, packed in the smallest availa ble fbga package with 51 2mb (64mb) capacity, is a single-die device with an embedded thin flash controller and flash memo ry. it uses toshiba?s cutting-edge, 0.13 nand-based multi-level cell (mlc) flash technology, enhanced by m-systems? proprietary x2 technolo gy. a dual-die device is available with single chip capacity of 1gb (128mb). mlc nand technology enables two b its of data to be stored on a single cell, cutting in half the physical die size. m-systems? pr oprietary x2 technology overcomes ml c-related error patterns and slow transfer rates by using a robust error de tection and correction (edc/ecc) mechanism. furthermore, it provides performance enhancem ent with multi-plane operation, dma support, turbo operation and multiburst operation. the combinati on of mlc and x2 technology results in a low- cost, minimal-sized flash disk that achieves unsurpassed reliability levels and enhanced performance. this breakthrough in performance, size and cost ma kes mobile diskonchip g3 the ideal solution for mobile product manufacturers who require high -capacity, small size, high-performance, and above all, high-reliability storage to enable ap plications such as enhanced multimedia messaging service (mms), gaming, video and personal info rmation management (pim) on mobile handsets and personal digital assistants (pdas). as with the mobile diskonchip plus family (g 2), mobile diskonchip g3 content protection and security-enabling features offer se veral benefits. two write- and read-p rotected partitions, with both software- and hardware-based protection, can be configured independen tly for maximum design flexibility. the 16-byte unique id (uid) identifies each flash device, eliminating the need for a separate id device on the mother board. the 6kb one time programmable (otp) area, written to once and then locked to prevent data and code fro m being altered, is ideal for storing customer and product-specific information. mobile diskonchip g3 512mb has a 2kb pr ogrammable boot block (4kb for mobile diskonchip g3 1gb). this block provides execut e in place (xip) functiona lity, enabling mobile diskonchip g3 to replace the boot device and func tion as the only non-volatile memory device on- board. eliminating the need for an additional boot device reduces hardware expenditures, board real estate, programming time, and logistics. m-systems? patented trueffs software technology fu lly emulates a hard disk to manage the files stored on mobile diskonchip g3. this transparen t file system management enables read/write operations that are identical to a standard, sector-based hard di sk. in addition, trueffs employs patented methods, such as virtual mapping, dynamic and static wear-leveling, and automatic block management to ensure high data reliabili ty and to maximize flash life expectancy.
mobile diskonchip g3 7 data sheet, rev. 1.0 91-sr-011-05-8l 2.2 512mb standard interface 2.2.1 pin/ball diagrams see figure 1 and figure 2 for the mobile diskon chip g3 512mb pinout/ballout for the standard interface. to ensure proper devi ce functionality, pins/balls marked rsrvd are reserved for future use and should not be connected. note: third-generation mobile diskonchip g3 is designed as a drop-in replacement for second-generation (g2) diskonchip plus products, assuming that the latter were integrated according to migration guide guidelines. refer to application note ap-doc-067, preparing your pcb footprint for the di skonchip bga migration path , for further information. tsop-i package 25 26 29 28 27 35 34 33 32 31 30 36 40 39 38 37 44 43 42 41 47 46 45 48 vss irq# d13 d14 d15 clk d8 d9 d10 d11 d12 vccq d5 d6 d7 vss d1 d2 d3 d4 id1 busy# d0 vss mobile diskonchip g3 512mb (64mb) 48-pin tsop-i 1 2 5 4 3 11 10 9 8 7 6 12 16 15 14 13 20 19 18 17 23 22 21 24 rstin# ce# a12 oe# we# a6 a7 a8 a9 a10 a11 vcc a3 a4 a5 vss rsrvd a0/dpd a1 a2 lock# if_cfg dmarq# id0 figure 1: tsop-i pinout for standard inte rface (mobile diskonchip g3 512mb)
mobile diskonchip g3 8 data sheet, rev. 1.0 91-sr-011-05-8l 7x10 fbga package m a b c d e f g h j k l m 1 2 3 4 5 6 7 8 m m m a7 a rsrvd rsrvd we# a8 a11 m m m m m m m m a6 a3 rsrvd rstin# rsrvd rsrvd a12 rsrvd a5 a2 rsrvd busy# rsrvd a9 lock# rsrvd a4 a1 if_cfg m m a10 id0 irq# vss a0/ dpd d1 m m d6 dmarq# id1 oe# ce# d9 d3 d4 d13 d15 rsrvd d0 rsrvd d10 vcc vccq d12 d7 vss d8 d2 d11 clk d5 d14 m m m m m m m m m m m m figure 2: 7x10 fbga ballout for standard in terface (mobile diskonchip g3 512mb)
mobile diskonchip g3 9 data sheet, rev. 1.0 91-sr-011-05-8l 2.2.2 system interface see figure 3 for a simplified i/o diagram for a standard interface of mobile diskonchip g3 512mb. mobi l e diskonchip g3 rstin# busy# host system bus ce#, oe#, we# a [12:0] d[15:0] configurati on control system interface id[1:0] if_cfg lock# irq# clk dmarq# dpd figure 3: standard interface simplified i/o diagram (mobile diskonchip g3 512mb)
mobile diskonchip g3 10 data sheet, rev. 1.0 91-sr-011-05-8l 2.2.3 signal description mobile diskonchip g3 tsop-i and fbga packages support identical signals. the related pin and ball designations are listed in th e signal descriptions , presented in logic groups, in table 1 and table 2. tsop-i package table 1: signal descriptions for standard inte rface (mobile diskonchip 512mb tsop-i package) signal pin no. input type description signal type system interface a[12:6] a[5:0] 5-11 14-19 st address bus. a0 is multip lexed with the dpd pin. input d[15:8] 46-39 st, r8 data bus, high byte. not used and may be left floating when if_cfg is set to 0 (8-bit mode). input/ output d[7:0] 35-28 st data bus, low byte. input/ output ce# 2 st chip enable, active low input we# 3 st write enable, active low input oe# 4 st output enable, active low input configuration id[1:0] 26, 24 st identification. conf iguration control to support up to four chips cascaded in the same memory window. chip 1 = id1, id0 = vss, vss (0,0); must be used for single-chip configuration chip 2 = id1, id0 = vss, vccq (0,1) chip 3 = id1, id0 = vccq, vss (1,0) chip 4 = id1, id0 = vccq, vccq (1,1) input lock# 23 st lock, active low. when active, provides full hardware data protection of selected partitions. input if_cfg 22 st interface configuration, 1(vccq) for 16-bit interface mode, 0 (vss) for 8-bit interface mode. input control busy# 27 od busy, active low, open drain. indicates that diskonchip is initializing and should not be accessed. a 10 k ? pull-up resistor is required if this pin drives an input. a 10 k ? pull-up resistor is recommended even if this pin is not used. output rstin# 1 st reset, active low. input clk 38 st system clock. input
mobile diskonchip g3 11 data sheet, rev. 1.0 91-sr-011-05-8l signal pin no. input type description signal type dmarq# 21 od dma request, active low. a 10 k ? pull-up resistor is required if this pin drives an input. a 10 k ? pull- up resistor is recommended even if this pin is not used. output irq# 47 od interrupt request, active low. a 10 k ? pull-up resistor is required if this pin drives an input. a 10 k ? pull-up resistor is recommended even if this pin is not used. output dpd 19 st deep power-down. used to enter and exit deep power-down mode. this pin is assigned a0 instead of dpd when working in 8-bit mode. input power vcc 12 - device core power supply. requires a 10 nf and 0.1 f capacitor. supply vccq 37 - i/o power supply. sets the logic 1 voltage level range of i/o pins. vccq may be either 2.5v to 3.6v or 1.65v to 2.0v. requires a 10 nf and 0.1 f capacitor. supply vss 13, 25, 36, 48 - ground. all vss pins must be connected. supply other rsrvd 20 - reserved. all rese rved signals are not connected internally and must be left floating to guarantee forward compatibility wi th future products. the following abbreviations are used: in - standard (non-schmid t) input, st - schmidt trigger input, od - open drain output, r8 - nominal 22k pull-up resistor, enabled only for 8-bit interface mode (if_cfg input is 0)
mobile diskonchip g3 12 data sheet, rev. 1.0 91-sr-011-05-8l 7x10 fbga package table 2: signal descriptions for standard interfac e (mobile diskonchip 512mb g3 7x10 fbga package) signal ball no. input type description signal type system interface a[12:11] a[10:8] a[7:4] a[3:0] d7, c7 f6, e6, c6 c2, d2, e2, f2 d1, e1, f1, g1 st address bus. a0 is multip lexed with the dpd ball. input d[15:14] d[13:12] d[11:8] h7, k7 h6, j6 k4, j3, h3, k2 st, r8 data bus, high byte. not used and may be left floating when if_cfg is set to 0 (8-bit mode). input/ output d[7:6] d[5:3] d[2:0] j7, g6 k6, h5, h4 k3, g3, j2 st data bus, low byte. input/ output ce# h1 st chip enable, active low input oe# h2 st write enable, active low input we# c5 st output enable, active low input configuration id[1:0] g8, f7 st identification. c onfiguration control to support up to four chips cascaded in the same memory window. chip 1 = id1, id0 = vss, vss (0,0); must be used for single chip configuration chip 2 = id1, id0 = vss, vccq (0,1) chip 3 = id1, id0 = vccq, vss (1,0) chip 4 = id1, id0 = vccq, vccq (1,1) input lock# e7 st lock, active low. when active, provides full hardware data protection of selected partitions. input if_cfg f3 st interface configuration, 1 (vccq) for 16-bit interface mode, 0 (vss) for 8-bit interface mode. input control busy# e4 od busy, active low, open drain. indicates that diskonchip is initializing and should not be accessed. a 10 k ? pull-up resistor is required if this ball drives an input. a 10 k ? pull-up resistor is recommended even if this ball is not used. output rstin# d4 st reset, active low. input clk k5 st system clock. input dmarq# g7 od dma request, active low. a 10 k ? pull-up resistor is required if this ball drives an input. a 10 k ? pull- up resistor is recommended even if this ball is not used. output
mobile diskonchip g3 13 data sheet, rev. 1.0 91-sr-011-05-8l signal ball no. input type description signal type irq# f8 od interrupt request, active low. a 10 k ? pull-up resistor is required if this ball drives an input. a 10 k ? pull-up resistor is recommended even if this ball is not used. output dpd g1 st deep power-down. used to enter and exit deep power-down mode. this ball is assigned a0 instead of dpd when working in 8-bit mode. input power vcc j4 - device supply. requires a 10 nf and 0.1 f capacitor. supply vccq j5 - i/o power supply. sets the logic 1 voltage level range of i/o balls. vccq may be either 2.5v to 3.6v or 1.65v to 2.0v. requires a 10 nf and 0.1 f capacitor. supply vss g2, j8 - ground. all vss balls must be connected. supply other rsrvd see figure 2 - reserved. a ll reserved signals are not connected internally and must be left floating to guarantee forward compatibility wi th future products. m - mechanical. these balls are for mechanical placement, and are not connected internally. a - alignment. this ball is for device alignment and is not connected internally. the following abbreviations are used: in - standard (non-schmid t) input, st - schmidt trigger input, od - open drain output, r8 - nominal 22k pull-up resistor, enabled only for 8-bit interface mode (if_cfg input is 0)
mobile diskonchip g3 14 data sheet, rev. 1.0 91-sr-011-05-8l 2.3 1gb standard interface 2.3.1 ball diagram see figure 4 for the mobile diskonchip g3 1gb standard interface ballout. to ensure proper device functionality, balls marked rsrvd are reserv ed for future use and should not be connected. note: mobile diskonchip g3 1gb is designed as a drop-in replacement for mobile diskonchip g3 512 mb, assuming that the board was desi gned according to migration guide guidelines. refer to applicati on note ap-doc-067, preparing your pcb footprint for the diskonchip bga migration path , for further information. 9x12 fbga package m m m vss a8 a9 d12 d5 rsrvd rsrvd rsrvd d10 d2 d0 oe# vss m a b c d e f g h j k l m 1 2 3 4 5 6 7 8 9 10 rsrvd rsrvd rsrvd a12 we# rsrvd a11 rstin# rsrvd lock# a1 a2 a3 dmarq# busy# irq# id0 rsrvd a4 a5 a6 a7 rsrvd id1 d4 d15 a0/ dpd d3 ce# d1 if_cfg rsrvd m m d8 clk d11 vcc vccq d7 d14 d6 d9 d13 a10 a m m m m m m figure 4 ballout for standard interface (mobile diskonchip g3 1gb 9x12 fbga package)
mobile diskonchip g3 15 data sheet, rev. 1.0 91-sr-011-05-8l 2.3.2 system interface see figure 5 for a simplified i/o diagram for a st andard interface of mobile diskonchip g3 1gb. mobi l e diskonchip g3 rstin# busy# host system bus ce#, oe#, we# a [12:0] d[15:0] configurati on control system interface id[1:0] if_cfg lock# irq# clk dmarq# dpd figure 5: standard interface simplified i/o diagram (mobile diskonchip g3 1gb)
mobile diskonchip g3 16 data sheet, rev. 1.0 91-sr-011-05-8l 2.3.3 signal description 9x12 fbga package table 3: signal descriptions for standard interfac e (mobile diskonchip g3 1gb 9x12 fbga package) signal ball no. input type description signal type system interface a[12:11] a[10:8] a[7:4] a[3:0] d8, c8 f7, e7, c7 c3, d3, e3, f3 d2, e2, f2, g2 st address bus. a0 is multip lexed with the dpd ball. input d[15:14] d[13:12] d[11:8] h8, k8 h7, j7 k5, j4, h4, k3 st, r8 data bus, high byte. not used and may be left floating when if_cfg is set to 0 (8-bit mode). input/ output d[7:6] d[5:3] d[2:0] j8, g7 k7, h6, h5 k4, g4, j3 st data bus, low byte. input/ output ce# h2 st chip enable, active low. input oe# h3 st write enable, active low. input we# c6 st output enable, active low. input configuration id[1:0] g9, f8 st identification. c onfiguration control to support up to two chips cascaded in the same memory window. chip 1 = id1, id0 = vss, vss (0,0); must be used for single chip configuration chip 2 = id1, id0 = vccq, vccq (1,1) input lock# e8 st lock, active low. when active, provides full hardware data protection of selected partitions. input if_cfg f4 st interface configuration, 1 (vccq) for 16-bit interface mode, 0 (vss) for 8-bit interface mode. input control busy# e5 od busy, active low, open drain. indicates that diskonchip is initializing and should not be accessed. a 10 k ? pull-up resistor is required if this ball drives an input. a 10 k ? pull-up resistor is recommended even if this ball is not used. output rstin# d5 st reset, active low. input clk k6 st system clock. input dmarq# g8 od dma request, active low. a 10 k ? pull-up resistor is required if this ball drives an input. a 10 k ? pull- up resistor is recommended even if this ball is not used. output
mobile diskonchip g3 17 data sheet, rev. 1.0 91-sr-011-05-8l signal ball no. input type description signal type irq# f9 od interrupt request, active low. a 10 k ? pull-up resistor is required if this ball drives an input. a 10 k ? pull-up resistor is recommended even if this ball is not used. output dpd g2 st deep power-down. used to enter and exit deep power-down mode. pin is assigned a0 instead of dpd when working in 8-bit mode. input power vcc j5 - device supply. requires a 10 nf and 0.1 f capacitor. supply vccq j6 - i/o power supply. sets the logic ?1? voltage level range of i/o balls. vccq may be either 2.5v to 3.6v or 1.65v to 2.0v. requires a 10 nf and 0.1 f capacitor. supply vss g3, j9 - ground. all vss balls must be connected. supply other rsrvd see figure 2 - reserved. a ll reserved signals are not connected internally and must be left floating to guarantee forward compatibility wi th future products. m - mechanical. these balls are for mechanical placement, and are not connected internally. a - alignment. this ball is for device alignment and is not connected internally. the following abbreviations are used: in - standard (non-schmid t) input, st - schmidt trigger input, od - open drain output, r8 - nominal 22k pull-up resistor, enabled only for 8-bit interface mode (if_cfg input is 0)
mobile diskonchip g3 18 data sheet, rev. 1.0 91-sr-011-05-8l 2.4 512mb multiplexed interface 2.4.1 pin/ball diagram see figure 6 and figure 7 for the mobile diskonchip g3 512mb pinout/ballout for the multiplexed interface. to ensure proper devi ce functionality, pins/balls marked rsrvd are reserved for future use and should not be connected. note: third-generation mobile diskonchip g3 is designed as a drop-in replacement for second- generation (g2) diskonchip plus products, assumi ng that the latter were integrated according to migration guide guidelines. refe r to application note ap-doc-067, preparing your pcb footprint for the diskonchip bga migration path , for further information. tsop-i package 25 26 29 28 27 35 34 33 32 31 30 36 40 39 38 37 44 43 42 41 47 46 45 48 vss irq# ad13 ad14 ad15 clk ad8 ad9 ad10 ad11 ad12 vccq ad5 ad6 ad7 gnd ad1 ad2 ad3 ad4 avd# busy# ad0 vss mobile diskonchip g3 512mb 48-pin tsop-i 1 2 5 4 3 11 10 9 8 7 6 12 16 15 14 13 20 19 18 17 23 22 21 24 rstin# ce# vss oe# we# vss vss vss vss vss vss vcc vss vss vss vss nc dpd vss vss lock# vccq dmarq# id0 figure 6: pinout for multiplexed interface (m obile diskonchip 512mb tsop-i package)
mobile diskonchip g3 19 data sheet, rev. 1.0 91-sr-011-05-8l 7x10 fbga package m a b c d e f g h j k l m 1 2 3 4 5 6 7 8 m m m vss a rsrvd rsrvd we# vss vss m m m m m m m m vss vss rsrvd rstin# rsrvd rsrvd vss rsrvd vss vss rsrvd busy# rsrvd vss lock# rsrvd vss vss vccq m m vss id0 irq# vss dpd ad1 m m ad6 dmarq# avd# oe# ce# ad9 ad3 ad4 ad13 ad15 rsrvd ad0 rsrvd ad10 vcc vccq ad12 ad7 vss ad8 ad2 ad11 clk ad5 ad14 m m m m m m m m m m m m figure 7 ballout for multiplexed interface (m obile diskonchip 512mb 7x10 fbga package)
mobile diskonchip g3 20 data sheet, rev. 1.0 91-sr-011-05-8l 2.4.2 system interface see figure 8 for a simplified i/o diagram. mobile di skonchi p g3 rsti n# dmarq# host system bus ce#, oe#, we# a d[15:0] confi gurati on control system interface id0 lock# a vd# irq# busy# clk dpd figure 8: multiplexed interface simplified i/o diagram
mobile diskonchip g3 21 data sheet, rev. 1.0 91-sr-011-05-8l 2.4.3 signal description mobile diskonchip g3 512mb tsop-i and 7x10 fbga packages support identical signals in the multiplexed interface. the related pin/ball designa tions are listed in the signal descriptions, presented in logic groups, in table 4 and table 5. tsop-i package table 4: signal descriptions for multiplexed inte rface (mobile diskonchip g3 512mb tsop-i package) signal pin no. input type description signal type system interface ad[15:0] 28-35, 39-46 st multiplexed bus. address and data signals. input/ output ce# 2 st chip enable, active low. input we# 3 st write enable, active low. input oe# 4 st output enable, active low. input configuration avd# 26 st set multiplexed interface. input id0 24 st identification. configuratio n control to support up to two chips cascaded in the same memory window. chip 1 = id0 = vss; must be used for single-chip configuration chip 2 = id0 = vccq input lock# 23 st lock, active low. when active, provides full hardware data protection of selected partitions. input control busy# 27 od busy, active low, open dr ain. indicates that diskonchip is initializing and should not be accessed. a 10 k ? pull-up resistor is required if this pin drives an input. a 10 k ? pull-up resistor is recommended even if this pin is not used. output rstin# 1 st reset, active low. input clk 38 st system clock. input dmarq# 21 od dma request, active low. a 10 k ? pull-up resistor is required if this pin drives an input. a 10 k ? pull-up resistor is recommended even if this pin is not used. irq# 47 od interrupt request, active low. a 10 k ? pull-up resistor is required if this pin drives an input. a 10 k ? pull-up resistor is recommended even if this pin is not used. output dpd 19 st deep power-down. used to enter and exit deep power-down mode. multiplexed with a0 when working in 16-bit mode. input
mobile diskonchip g3 22 data sheet, rev. 1.0 91-sr-011-05-8l signal pin no. input type description signal type power vccq 37,22 - i/o power supply. sets the logic 1 voltage level range of i/o pins. vccq may be either 2.5v to 3.6v or 1.65v to 2.0v. requires a 10 nf and 0.1 f capacitor. supply vcc 12 - device core supply. requires a 10 nf and 0.1 f capacitor. supply vss 5-11, 14-18, 13, 25, 36, 48 - ground. all vss pins must be connected. supply reserved rsrvd 20 - reserved signal that is not connected internally and must be left floating to guarantee forward compatibility with future products. it should not be connected to arbitrary signals. the following abbreviations are used: in - standard (non-schmid t) input, st - schmidt trigger input, od - open drain output
mobile diskonchip g3 23 data sheet, rev. 1.0 91-sr-011-05-8l 7x10 fbga package table 5: signal descriptions for multiplexed in terface (mobile diskonchip g3 7x10 fbga package) signal ball no. input type description signal type s y stem interface ad[15:14] ad[13:12] ad[11:9] ad[8:6] ad[5:3] ad[2:0] h7, k7 h6, j6 k4, j3, h3 k2, j7, g6 k6, h5, h4 k3, g3, j2 st multiplexed bus. addr ess and data signals input/ output ce# h1 st chip enable, active low input oe# h2 st write enable, active low input we# c5 st output enable, active low input confi g u r ation avd# g8 st set multiplexed interface input id0 f7 st identification. configuratio n control to support up to two chips cascaded in the same memory window. chip 1 = id0 = vss; must be used for single-chip configuration chip 2 = id0 = vcc input lock# e7 st lock, active low. when active, provides full hardware data protection of selected partitions. input control busy# e4 od busy, active low, open dr ain. indicates that diskonchip is initializing and should not be accessed a 10 k ? pull-up resistor is required if this ball drives an input. a 10 k ? pull-up resistor is recommended even if this ball is not used. output rstin# d4 st reset, active low. input clk k5 st system clock. input dmarq# g7 od dma request, active low. a 10 k ? pull-up resistor is required if this ball drives an input. a 10 k ? pull-up resistor is recommended even if this ball is not used. output irq# f8 od interrupt request, active low. a 10 k ? pull-up resistor is required if this ball drives an input. a 10 k ? pull-up resistor is recommended even if this ball is not used. output dpd g1 st deep power-down. used to enter and exit deep power- down mode. pin is assigned a0 instead of dpd when working in 8-bit mode. input
mobile diskonchip g3 24 data sheet, rev. 1.0 91-sr-011-05-8l signal ball no. input type description signal type power vcc j4 - device core supply. requires a 10 nf and 0.1 f capacitor. supply vccq j5, f3 - i/o power supply. sets the logic 1 voltage level range of i/o balls. vccq may be either 2.5v to 3.6v or 1.65v to 2.0v. requires a 10 nf and 0.1 f capacitor. supply vss g2,j8, d7,c7,f6,e6, c6,c2,d2,e2 ,f2,d1,e1,f1 - ground. all vss pins must be connected. supply other rsrvd see figure 7 - reserved. all rese rved signals are not connected internally and must be left floating to guarantee forward compatibility with future products. m mechanical. these balls are for mechanical placement, and are not connected internally. a - alignment. this ball is for device alignment and is not connected internally. the following abbreviations are used: in - standard (non-schmid t) input, st - schmidt trigger input, od - open drain output
mobile diskonchip g3 25 data sheet, rev. 1.0 91-sr-011-05-8l 2.5 1gb multiplexed interface 2.5.1 ball diagram see figure 9 for the mobile diskonchip g3 1gb ( dual-die) ball diagram. to ensure proper device functionality, balls marked rsrv d are reserved for future us e and should not be connected. note: mobile diskonchip g3 1gb is designed as a drop-in replacement for mobile diskonchip g3 512mb, assuming that the board was de signed according to the migration guide guidelines. refer to app lication note ap-doc-067, preparing your pcb footprint for the diskonchip bga migration path , for further information. 9x12 fbga package m m m vss vss vss ad12 ad5 rsrvd rsrvd rsrvd ad10 ad2 ad0 oe# vss m a b c d e f g h j k l m 1 2 3 4 5 6 7 8 9 10 rsrvd rsrvd rsrvd vss we# rsrvd vss rstin# rsrvd lock# vss vss vss dmarq# busy# irq# id0(vss) rsrvd vss vss vss vss rsrvd avd# ad4 ad15 dpd ad3 ce# ad1 vccq rsrvd m m ad8 clk ad11 vcc vccq ad7 ad14 ad6 ad9 ad13 vss a m m m m m m figure 9: ballout for multiplexed interface (m obile diskonchip g3 1gb 9x12 fbga package)
mobile diskonchip g3 26 data sheet, rev. 1.0 91-sr-011-05-8l 2.5.2 system interface see figure 10 for a simplified i/o diagram. mobi l e di skonchi p g3 1gb rsti n# dmarq# host system bus ce#, oe#, we# ad[ 15: 0] conf i gurat i on cont rol system interface lock# avd# irq# busy# clk dpd id0 figure 10: multiplexed interface simplified i/o diagram
mobile diskonchip g3 27 data sheet, rev. 1.0 91-sr-011-05-8l 2.5.3 signal description 9x12 fbga package table 6: signal descriptions for multiplexed inte rface (mobile diskonchip g3 1gb 9x12 fbga package) signal ball no. input type description signal type s y stem interface ad[15:14] ad[13:12] ad[11:9] ad[8:6] ad[5:3] ad[2:0] h8, k8 h7, j7 k5, j4, h4 k3, j8, g7 k7, h6, h5 k4, g4, j3 st multiplexed bus. address and data signals input/ output ce# h2 st chip enable, active low input oe# h3 st write enable, active low input we# c6 st output enable, active low input confi g uration avd# g9 st set multiplexed interface input id0 f8 st identification. nc for mobile diskonchip g3 1gb. input lock# e8 st lock, active low. when active, provides full hardware data protection of selected partitions.. input control busy# e5 od busy, active low, open dr ain. indicates that diskonchip is initializing and should not be accessed. a 10 k ? pull-up resistor is required if this pin/ball drives an input. a 10 k ? pull-up resistor is recommended even if this pin/ball is not used. output rstin# d5 st reset, active low. input clk k6 st system clock. input dmarq# g8 od dma request, active low. a 10 k ? pull-up resistor is required if this pin/ball drives an input. a 10 k ? pull-up resistor is recommended even if this pin/ball is not used. output irq# f9 od interrupt request, active low. a 10 k ? pull-up resistor is required if this pin/ball drives an input. a 10 k ? pull-up resistor is recommended even if this pin/ball is not used. output dpd g2 st deep power-down. used to enter and exit deep power- down mode. multiplexed with a0 when working in 16-bit mode. input
mobile diskonchip g3 28 data sheet, rev. 1.0 91-sr-011-05-8l signal ball no. input type description signal type power vcc j5 - device core supply. requires a 10 nf and 0.1 f capacitor. supply vccq j6, f4 - i/o power supply. sets the logic ?1? voltage level range of i/o balls/pins. vccq may be either 2.5v to 3.6v or 1.65v to 2.0v. requires a 10 nf and 0.1 f capacitor. supply vss g3,j9, d8,c8,f7,e7, c7,c3,d3,e3 ,f3,d2,e2,f2 - ground. all vss pins must be connected. supply other rsrvd see figure 9 - reserved. all rese rved signals are not connected internally and must be left floating to guarantee forward compatibility with future products. m mechanical. these balls are for mechanical placement, and are not connected internally. a - alignment. this ball is for device alignment and is not connected internally. the following abbreviations are used: in - standard (non-schmid t) input, st - schmidt trigger input, od - open drain output, r8 - nominal 22k pull-up resistor, enabled only for 8-bit interface mode (if_cfg input is 0)
mobile diskonchip g3 29 data sheet, rev. 1.0 91-sr-011-05-8l 3. t heory of o peration 3.1 overview mobile diskonchip g3 consists of the following major functional blocks, as shown in figure 11. *addr[0] and dpd are multiplexed on the same ball/pin. figure 11: mobile diskonchip g3 simplif ied block diagram, standard interface these components are described briefly below a nd in more detail in the following sections. ? system interface for the host interface. ? configuration interface for configuring mobile diskonchip g3 to operate in 8-bit, 16-bit or 32-bit mode, cascaded configuration, hardware re ad/write protection and entering/exiting deep power-down mode. ? read/write protection and otp for advanced data/code security and protection. ? programmable boot block with xip functionality enhanced with a download engine (de) for system initialization capability. ? error detection and error correction code (edc/ecc) for on-the-fly error handling. ? data pipeline through which the data flows from the system to the nand flash arrays. ? control & status block that contains registers responsible for transferring the address, data and control information between the trueffs driver and the flash media . ? flash interface that interfaces to two nand flash planes.
mobile diskonchip g3 30 data sheet, rev. 1.0 91-sr-011-05-8l ? bus control for translating the host bus address, a nd data and control signals into valid nand flash signals. ? address decoder to enable the relevant unit inside th e diskonchip controller, according to the address range received from the system interface. 3.2 system interface 3.2.1 standard (nor-like) interface the system interface block provides an easy-to -integrate nor-like (also sram and eeprom- like) interface to mobile diskonchip g3, enabli ng it to interface with vari ous cpu interfaces, such as a local bus, isa bus, nor interface, sram interface, eeprom interface or any other compatible interface. in addition, the eeprom- like interface enables direct access to the programmable boot block to permit xip (ex ecute-in-place) functiona lity during system initialization. a 13-bit wide address bus enables access to the mobile diskonchip g3 8kb memory window (as shown in section 7.2). a 16-bit internal data bus is supported by parallel access to two 256mb flash planes (for 512mb single-die devices), each of which enables 8-bit access. this 16-bit data bus permits 16-bit wide access to the host. the chip enable (ce#), write enable (we#) and output enable (oe#) signals trigger read and write cycles. a write cycle occurs while both th e ce# and the we# inputs ar e asserted. similarly, a read cycle occurs while both the ce# and oe# input s are asserted. note th at mobile diskonchip g3 does not require a clock signal. it features a unique analog stat ic design, optimized for minimal power consumption. the ce#, we# and oe# signals trigger the controller (e.g., system interface block, bus control and data pipeline) and flash access. the reset in (rstin#) and busy (busy#) cont rol signals are used in the reset phase. the interrupt request (irq#) signal can be used when long i/o operations, such as block erase, delay the cpu resources. the signal is also asserted when a data protection violation has occurred. this signal frees the cpu to run other tasks, continuing read/write ope rations with mobile diskonchip g3 only after the irq# signal has b een asserted and an interrupt handling routine (implemented in the os) has been called to return control to the trueffs driver. the dmarq# output is used to control multi-page dma operations, and the clk input is used to support multiburst operation when reading flash data. see section 4.1 for further information. 3.2.2 multiplexed interface in this configuration, the address and data signals are multiplexed. the id[1] input is driven by the host avd# signal, and the d[15:0] pins/balls, used for both address inputs and data, are connected to the host ad[15:0] bus. while avd# is asserted, th e host drives ad[11:0] w ith bits [12:1] of the address. host signals ad[15:12] are not signi ficant during this part of the cycle. this interface is automatically used when a falling edge is detected on id[1]. this edge must occur after rstin# is negated and before the first read or write cycle to the controller. when using a multiplexed interface, the value of id[1] is interna lly forced to logic-0. the only possible device id values are 0 and 1; therefore, only up to tw o mobile diskonchip g3 512mb devices may be
mobile diskonchip g3 31 data sheet, rev. 1.0 91-sr-011-05-8l cascaded in multiplexed configuration (dual-die m obile diskonchip g3 1gb cannot be cascaded when used in a multiplexed interface). 3.3 configuration interface the configuration interface block enables the designer to configure mobile diskonchip g3 to operate in different modes. the id[1:0] signals are used in a cascaded configuration (refer to section 10.6), the dpd signal is us ed to enter and exit deep powe r-down mode (see section 6.3), the lock# signal is used for hardware write/read protection, and the if_cfg signal is used to configure 8/16-bit access. 3.4 protection and security-enabling features the protection and security-enabl ing block, consisting of read/write protection, uid and an otp area, enables advanced data and code security an d content protection. located on the main route of traffic between the host and the flash, this block monitors and controls all data and code transactions to and from mobile diskonchip g3. 3.4.1 read/write protection data and code protection is impl emented through a prot ection state machine (psm). the user can configure one or two independent ly programmable areas of the flash memory as read protected, write protected, or read/write protected. a protected partition may be protected by e ither/both of these hardware mechanisms: ? 64-bit protection key ? hard-wired lock# signal if the lock option is enabled (by means of so ftware) and the lock# signal is asserted, the protected partition has an additiona l hardware lock that prevents re ad/write access to the partition, even with the use of the correct protection key. the lock# signal must be asserted during formatting (and later when the partition is defined as changeable) to enable the additional hardware safety lock. only one partition can be defined as ?changeable ?; i.e., its password a nd attributes are fully configurable at any time (from read to write, both or none and vise versa). note that ?un- changeable? partition attributes cannot be changed unless the media is reformatted. the size and protection attributes of the protecte d partition are defined dur ing the media-formatting stage. in the event of an attempt to bypass the protectio n mechanism, illegally m odify the protection key or in any way sabotage the confi guration parameters, the entire mobile diskonchip g3 becomes both read and write protected, and is completely inaccessible. for further information on hardware protection, please refer to the trueffs software development kit (sdk) developer guide. 3.4.2 unique identification (uid) number each mobile diskonchip g3 is assigned a 16- byte uid number. burned onto the flash during production, the uid cannot be altered and is unique worldwide. the uid is essential in security-
mobile diskonchip g3 32 data sheet, rev. 1.0 91-sr-011-05-8l related applications, and can be used to identify end-user produc ts in order to fight fraudulent duplication by imitators. 3.4.3 one-time programmable (otp) area the 6kb otp area is user programmable for comple te customization. the user can write to this area once, after which it is automatically and perm anently locked. after it is locked, the otp area becomes read only, just like a rom device. typically, the otp area is used to store custom er and product information such as: product id, software version, production data, cust omer id and tracking information. 3.4.4 one-time write (rom-like) partition a single partition in the mobile diskonchip g3 can be set as one-time write. after it is locked, this partition becomes read only, just like a rom de vice. its capacity is defined during the media- formatting stage. 3.4.5 sticky lock (slock) the boot partition can be locked automatically by hardware after the boot phase is completed and the device is in normal mode. this is done by se tting the sticky lock (slo ck) bit in the output control register to 1. this has the same effect as asserting the lock# signal. once set, slock can only be cleared by asserting the rstin# input. like the lock# input, assertion of this bit prevents the protection key from disabling the protection for a given partition. there is no need to mount the boot partition before calling a hardware protection routine. upon reset, the boot partition is unlocked for the duration of the boot phase, and is automatically locked once this phase is over. this provides a hi gh level of protection to the boot code, while still enabling an easy method for field and remote upgrades. 3.5 programmable boot block with ex ecute in place (x ip) functionality the programmable boot block with xip functionality enables mobile diskonchip g3 to act as a boot device in addition to performi ng flash disk data storage functi ons. this eliminates the need for expensive, legacy nor flash or a ny other boot device on the motherboard. the programmable boot block on m obile diskonchip g3 512mb is 2kb in size (4kb for dual-die 1gb devices). the download engine (de), describe d in the next section, e xpands the functionality of this block by copying the boot code from the flash into the boot block. diskonchip g3 512mb devices may be cascaded in or der to form a larger flash disk. when mobile diskonchip g3 512mb is connected with a standard nor-like interface, up to four devices may be cascaded to create a 2gb flash disk. when mobile diskonchip g3 512mb is connected with a multiplexed interface, up to two devices may be cascaded to create a 1gb flash disk. notes: 1. when more than one mobile di skonchip g3 512mb are cascaded, a maximum boot block of 4kb is available. the programmable boot block of each device is mapped to a unique address space. 2. the programmable boot block size available for mobile diskonchip g3 1gb (dual-die) is 4 kb.
mobile diskonchip g3 33 data sheet, rev. 1.0 91-sr-011-05-8l 3.6 download engine (de) upon power-up or when the rstin# signal is assert ed, the de automatically downloads the initial program loader (ipl) to the pr ogrammable boot block. the ipl is responsible for starting the booting process. the download process is quick, and is designed so that when the cpu accesses mobile diskonchip g3 for code execution, the ip l code is already located in the programmable boot block. in addition, the de downloads th e data protection rules from th e flash to the protection state machines (psm), so that mobile diskonchip g3 is secure and protected from the first moment it is active. during the download process, mobile diskonchip g3 asserts the busy# signal to indicate to the system that it is not yet ready to be acce ssed. once busy# is negated, the system can access mobile diskonchip g3. a failsafe mechanism prevents impr oper initialization due to a faulty vcc or invalid assertion of the rstin# input. another failsafe mechanism is designed to overcome po ssible nand flash data errors. it prevents internal registers from po wering up in a state that bypasses the intended data protection. in addition, any attempt to sabotage the data structures ca uses the entire diskonchip to become both read and write protec ted, and completely inaccessible. 3.7 error detection code/erro r correction code (edc/ecc) because nand-based mlc flash is prone to errors, it requires unique erro r-handling capability. m- systems? x2 technology implements 4-bit error de tection code/error corre ction code (edc/ecc), based on a patented combination of bose, ch audhuri and hocquenghem (bch) and hamming code algorithms. error detection code (edc) is impl emented in hardware to optimize performance, while error correction code (ecc) is performed in software, when requ ired, to save silicon costs. each time a 512-byte page is written, additional pari ty bits are calculated and written to the flash. each time data is read from the flash, the parity b its are read and used to calculate error locations. the hamming code can detect 2 errors per page and correct 1 error per page. the bch code can detect and correct 4 errors per page. it can detect 5 errors per page with a probability of 99.9%. it ensures that the minimal amount of code required is used for detection and correction to deliver the required reliability without degrading performance. 3.8 data pipeline mobile diskonchip g3 uses a two-stage pipelin e mechanism, designed for maximum performance while enabling on-the-fly data manipulation, such as read/write protection and error detection/error correction. refer to technical note tn-doc-014, pipeline mechanism in diskonchip , for further information. 3.9 control and status the control and status block cont ains registers responsible for tr ansferring address, data and control information between the diskonchip tr ueffs driver and the flash media. additional registers are used to monitor the status of the flash media (ready/busy) and the diskonchip controller. for further inform ation on the diskonchip registers, refer to section 8.
mobile diskonchip g3 34 data sheet, rev. 1.0 91-sr-011-05-8l 3.10 flash architecture mobile diskonchip g3 512mb consists of two 2 56mb flash planes that consist of 1024 blocks each, organized in 64 pages, as follows: ? page ? each page contains 512 bytes of user data a nd a 16-byte extra area th at is used to store flash management and edc/ecc signat ure data, as shown in figure 12. ? block ? each block contains 64 pages (total of 256kb), as shown in figure 13. a block is the minimal unit that can be erased, and is sometimes referred to as an erase block. note: since the device works with multiple planes, the operational block size is 512kb, as described in the next section. 16 bytes 512 bytes user data flash management & ecc/edc signature 0.5 kb figure 12: page structure 16 bytes 512 bytes page 0 page 1 256 kb page 63 page 62 figure 13: block structure parallel multi-plane access the two 256mb flash planes operate in parallel, th ereby providing a true 32 -bit internal data bus and four times the read, write and erase performance. two page s on different planes can be concurrently read or written if they have the same offset within their respective units, even if the units are unaligned. bad units are mapped individually on each plane by enabling unaligned unit access, as shown in figure 14. good units can therefore be aligned or unaligned, minimizing the effects of bad units on the media. without this capability, a bad unit in one plane would cause a good unit in the second plane to be tagged as a bad unit, making it unusabl e. this customized method of bad unit handling for two planes enhances data reliability without adversely aff ecting performance.
mobile diskonchip g3 35 data sheet, rev. 1.0 91-sr-011-05-8l bad unit good unit good unit 16-bit data bus bad unit u n a l i g n e d u n i t 16-bit data bus flash plane 2 flash plane 1 internal bus good unit good unit aligned unit good unit good unit aligned unit ~ ~ ~ ~ ~ ~ ~ ~ good unit good unit aligned unit good unit good unit aligned unit good unit good unit aligned unit figure 14: unaligned multi-plane access
mobile diskonchip g3 36 data sheet, rev. 1.0 91-sr-011-05-8l 4. x 2 t echnology mobile diskonchip g3 enhances performa nce using various proprietary techniques: ? parallel access to the separate 256mb flash plan es, thereby providing an internal 32-bit data bus. see section 3.10 for further information. ? multiburst operation to read larg e chunks of data, providing a mult iburst read speed of up to 80 mb/sec. ? dma operation to release the cpu for other task s in coordination with the platform?s dma controller. this is especially useful during the boot stage. up to 64kb of data can be transferred during a dma operation. ? turbo operation to enhance read access time from 55 ns to 33 ns (standard interface, access to flash addresses). 4.1 multiburst operation multiburst operation is especially effective for large file read s that are typical during boot-up. during multiburst operation, data is read from the two flash planes in parallel through a 32-bit wide internal flash interface. data is read by the host one 16-bit wo rd after another using the clk input, resulting in a multiburst read mode of up to 80 mb/sec. multiburst operation can only be performed on hosts that support bur st reads. see figure 15 below.
mobile diskonchip g3 37 data sheet, rev. 1.0 91-sr-011-05-8l flash plane w o r d 0 flash plane w o r d 1 32-bit data mux 16-bit to host 16-bit data 16-bit data word 0 word 1 fifo 32-bit transfer 32-bit transfer data transfer from flash planes to fifo /flash_oe internal data transfers 16-bit transfer 16-bit transfer 16-bit transfer 16-bit transfer /diskonchip_oe data transfer from fifo to host external data transfers figure 15: multiburst operation note: mobile diskonchip g3 does not support multiburst write operations. multiburst operation is controlled by 5 bits in th e multiburst mode control register: burst_en, clk_inv, latency, hold and length. for full de tails on this register, please refer to section 8. multiburst mode read cycles are supported via the clk input, which is enabled by setting the burst_en bit in the multiburst mode control register. to determine whether the rising or falling edge of the clk input is sampled (called clk0), the clk_inv bit in the multiburst mo de control register must be specified. when the clk_inv bit is set to 0, ce# and oe# are sampled on the rising edge of clk; when the clk_inv bit is set to 1, sampling is done on the falling edge of clk. notes: 1. when the clk_inv bit is set to 1, sa mpling is done on the falling edge of clk, and an additional half-clock cycle of latency is incurred. data continues to be output on d[15:0] on the rising edge of clk. 2. the clk input is disabled upon the assertion of the rstin# input and may therefore be left floating.
mobile diskonchip g3 38 data sheet, rev. 1.0 91-sr-011-05-8l the latency bit is the third bit that must be se t in the multiburst mode control register. when the latency bit is set to 0, the host can latch th e first 16-bit data word two clock cycles after clk0. this time can be extended by up to seven clock cycles by programming the latency bit. after latching the first word, additional 16-bit data words can be latched on each subsequent clock cycle. the hold bit in the multiburst mode control regist er can be set to hold each data word valid for two clock cycles rather than one. the length bit in the multiburst mode control regi ster must be programmed with the length of the burst to be performed. as read cycles from the flash are volatile, each burst cycle must read exactly this number of words. the clk input can be toggled continuously or can be halted. when halting the clk input, the following guidelines must be observed: ? after asserting oe# and ce#, latency + 2 clk cycles are required prior to latching the first word (2.5 clk cycles if clk_inv is set to 1). ? if the hold bit is set to 0, the host must pr ovide one rising clk edge for each word read, except for the last word latched, for wh ich clk does not need to be toggled. ? if the hold bit is set to 1, the host must pr ovide two rising clk edges for each word read, except for the last word, for which the second of the two clk rising edges is not required. ? subsequent toggling of the clk is optional. 4.2 dma operation mobile diskonchip g3 provides a dmarq# output th at enables up to 64kb to be read from the flash by the host dma controller. during dma ope ration, the dmarq# output is used to notify the host dma controller that the ne xt flash page is ready to be read, and the irq# pin indicates whether an error occurred while re ading the data from the flash or the end of the dma transfer was reached. the dmarq# output sensitivity is chosen by setting the edge bit in the dma control register[0]: ? edge ? the dmarq# output pulses to logic 0 for 250~500 nsec to indicate to the dma controller that a flash page is ready to be read. the edge bit is set to 1 for this mode. ? level ? the dmarq# output is assert ed to initiate the block transfer and returns to the negated state at the end of each block transfer. the edge bit is set to 0 for this mode. the following steps are required to initiate a dma operation: 1. initialize the platform?s dma controller to transfer 512 bytes upon each assertion of the dmarq# output. if the dma controller supports an edge-sensitive dmarq# signal, then initialize the dma controller to transfer 512 bytes upon each dma request. if the dma controller supports a leve l-sensitive dmarq# signal, then initialize the dma controller to transfer data while dmarq# is asserted.
mobile diskonchip g3 39 data sheet, rev. 1.0 91-sr-011-05-8l 2. set the bits in the interrupt control register (s ee section 8) to enable interrupts on an ecc error and at the end of the dma operation. 3. write to the dma control register[0] to set th e dma_en bit, the edge bit and the number of sectors (sector_count bit) to be transferred to the host. at th is point, mobile diskonchip g3 generates a dma request to indicate to the host that it is rea dy to transfer data. 4. the host dma controller reads one sector (512 bytes) of data from mobile diskonchip g3. 5. if an ecc error is detected, an interrupt is gene rated (irq# signal asserted), the transfer of data is halted and control is returned to the host. if no ecc error is detected, a dma request is initiated (dmarq# signal asserted) and th e next sector is read by the host. 6. the process continues until the last sector is read, after which mobile diskonchip g3 generates an interrupt (i rq# signal asserted) to indicate that it has transferred the last byte. notes: 1. mobile diskonchip g3 generates a dma request (dmarq# si gnal asserted) after the last byte is read. it may therefore be nece ssary to clear the final dma request from the dma controller. 2. dma operation may be aborted after tran sferring each 512-byte block (step 4) by clearing the dma_en bit in the dma control register[0]. 4.3 combined multiburst mode and dma operation when using multiburst mode and dma operation t ogether, and an interrupt is generated (irq# signal asserted), the download status register cannot be polled, as it will not comply with the multiburst mode timing sp ecification. the following sequence is therefore required to respond to an interrupt request while in multiburst mode: ? perform 7 write cycles to the nop register. ? turn off multiburst mode by writing to the multiburst mode control register. 4.4 turbo operation in order to provide faster read access time, mobi le diskonchip g3 can be configured for turbo operation by enabling the d[15:0] output buffers immediately afte r the assertion of oe# and ce#. enter turbo operation by setting the turbo bit in the output control register. for timing specifications for turbo operation, see section 11.3. since the read access time for the programmable boot block is slow er than the read access time for the registers, bus contention ma y occur when reading from the programmable boot block during system boot. it is therefore not recommended to use turbo operation duri ng boot, but only after the system is up and running and mobile diskon chip g3 is being used as a flash disk.
mobile diskonchip g3 40 data sheet, rev. 1.0 91-sr-011-05-8l 5. h ardware p rotection 5.1 method of operation mobile diskonchip g3 enables the user to define two partitions that ar e protected (in hardware) against any combination of read or write operations. the two protec ted areas can be configured as read protected or write protecte d, and are protected by a protecti on key (i.e. password) defined by the user. each of the protected areas can be c onfigured separately and can function separately, providing maximum flexibility for the user. the size and protection attributes (protection key, read, write, changeable, lock) of the protected partition are defined in the media formatting stage (dformat utility or the format function in the trueffs sdk). in order to set or remove read/write protection, th e protection key (i.e., password) must be used, as follows: ? insert the protection key to remove read/write protection. ? remove the protection key to set read/write protection. mobile diskonchip g3 has an a dditional hardware safety measure. if the lock op tion is enabled (by means of software) and the lock# signal is a sserted, the protected pa rtition has an additional hardware lock that prevents read /write access to the partition, ev en with the use of the correct protection key. the lock# signal must be a sserted during dformat (and later when the partition is defined as changeable) to enab le the additional hard-wired safety lock. it is possible to set the lock option for one sessi on only; that is, until the next power-up or reset. this sticky lock feature can be useful when the boot code in the boot partit ion must be read/write protected. upon power-up, the boot code must be unpr otected so the cpu can run it directly from mobile diskonchip g3. at the end of the boot pr ocess, protection can be set until the next power- up or reset. setting the sticky lock (slock) bit in the output control register to 1 has the same effect as asserting the lock# signal. once set, slock can only be cleared by asserting the rstin# input. like the lock# input, the assertion of this bit prevents the protection key from disabling the protection for a given partition. for more inform ation, see section 3.4.5. the target partition does require mounting before calling a hardware protection routine. the only way to read or write from a protected partition is to use insert the key (even dformat does not remove the protection). this is also true for modifying its attributes (prote ction key, read, write and lock). read/write protection is di sabled in each of the following events: ? power-down ? change of any protection attribute (not necessarily in the same partition) ? write operation to the ipl area ? removal of the protection key. for further information on hardware protection, please refer to the trueffs software development kit (sdk) developer guide.
mobile diskonchip g3 41 data sheet, rev. 1.0 91-sr-011-05-8l 5.2 low-level structure of the protected area the first five blocks in mobile diskonchip g3 contain foundr y information, the data protect structures, ipl code, and bad bloc k mapping information. see figure 16. bad block table and factory-programmed uid data protect structure 0 pages 0-5 pages 8-31 otp data protect structure 1 and ipl code block 0 block 1+2 block 3+4 figure 16: low level structure of mobile diskonchip g3 blocks 0-4 in mobile diskonchip g3 contain the following information: block 0 o bad block table (page 4). contains the ma pping information on unusable erase units on the flash media. o uid (16 bytes). this number is written dur ing the manufacturing stage, and cannot be altered at a later time. o customer otp (occupies pages 8-31). the otp area is written once and then locked. block 1 and 2 o data protect structure 0. th is structure contains configuration information on one of the two user-defined protected partitions. bl ock 2 is a copy of block 1 for redundancy purposes.
mobile diskonchip g3 42 data sheet, rev. 1.0 91-sr-011-05-8l block 3 and 4 o data protect structure 1. th is structure contains configuration information on one of the two user-defined protected partitions. o ipl code (2kb). this is the boot code that is downloaded by the de to the internal boot block. o block 4 is a copy of block 3 for redundancy purposes.
mobile diskonchip g3 43 data sheet, rev. 1.0 91-sr-011-05-8l 6. m odes of o peration mobile diskonchip g3 operates in one of three basic modes: ? normal mode ? reset mode ? deep power-down mode the current mode of the chip can always be determined by reading the diskonchip control register. mode changes can occur due to any of the following events: ? assertion of the rstin# signal sets the device in reset mode. ? during power-up, boot detector circuitr y sets the device in reset mode. ? a valid write sequence to mobile diskonchip g3 sets the device in normal mode. this is done automatically by the trueffs driver on power-up (reset sequence end). ? switching back from normal mode to reset mo de can be done by a valid write sequence to mobile diskonchip g3, or by triggering the boo t detector circuitry (via a soft reset). ? deep power-down ? a valid write sequence, initiated by software, sets the device from normal mode to deep power-down mode. four read cycles from offs et 0x1fff set the device back to normal mode. alternately, the device can be set back to no rmal mode with an extended access time during a read from the programmable boot block. ? asserting the rstin# signal and holding it in this state while in normal mode puts the device in deep power-down mode. when rstin# is re leased, the device is set in reset mode. ? toggling the dpd signal as define d by the dpd control register. power off reset mode deep power-down mode normal mode power-up power-down assert rstin#, boot detect or software control power-down reset sequence end software control 4x read cycles from offset 0x1fff or extended read cycle power-down release rstin# assert rstin# assert rstin# figure 17: operation modes and related events
mobile diskonchip g3 44 data sheet, rev. 1.0 91-sr-011-05-8l 6.1 normal mode this is the mode in which sta ndard operations involving the flas h memory are performed. normal mode is entered when a valid write sequence is sent to the diskonchip control register and control confirmation register. the boot detect or circuit triggers the software to set the device to normal mode. a write cycle occurs when both the ce# and we# i nputs are asserted. similarly, a read cycle occurs when both the ce# and oe# inputs are asserted. becau se the flash controller generates its internal clock from these cpu cycles and some read operations return volatile data, it is essential that the timing requirements specified in section 11.3 be met. it is also essential that read and write cycles not be interrupted by glitches or ringing on the ce#, we#, and oe# address inputs. all inputs to mobile diskonchip g3 are schmidt tri gger types to improve noise immunity. 6.2 reset mode in reset mode, mobile diskonchip g3 ignores all write cycles, exce pt for those to the diskonchip control register and control confir mation register. all register read cycles return a value of 00h. before attempting to perform a register read operation, the device is set to normal mode by trueffs software. 6.3 deep power-down mode while in deep power-down mode, mobile disk onchip g3?s quiescent power dissipation is reduced by disabling internal high current consumers (e.g. volta ge regulators, input buffers, oscillator etc.). the following signals are also disabled in this mode: ? standard interface : input buffers a[12:0], we#, d[15:0] and oe# (when ce# is negated) ? multiplexed interface : input buffers ad[15:0], avd#, we# and oe# (when ce# is negated). to enter deep power-down mode, a proper sequence must be written to the mobile diskonchip g3 control registers and the ce# input must be negated. all other inputs should be vss or vcc. when in normal mode, asserti ng the rstin# signal and holding it in low state puts the device in deep power-down mode. when the rstin# signal is released, the device is set in reset mode. in deep power-down mode, write cy cles have no effect and read cy cles return indeterminate data (mobile diskonchip g3 does not drive the data bus). entering deep power-down mode and then returning to the previous mode does not affect the value of any register. to exit deep power-down mode, use one of the following methods: ? read four times from address 1fffh (program mable boot block). the data returned is undefined. ? perform a single read cycle from the programma ble boot block with an extended access time and address hold time as specified in the timing diagrams. the data returned will be correct. please note that this option can only be used w ith a standard interface, not with a multiplexed interface. ? toggle the dpd input as defined by the dpd control register.
mobile diskonchip g3 45 data sheet, rev. 1.0 91-sr-011-05-8l applications that use mobile disk onchip g3 as a boot device must ensure that the device is not in deep power-down mode before reading the boot v ector/instructions. this can be done by pulsing rstin# to the asserted state and waiting for th e busy# output to be negated, or by entering reset mode via software (the program mable boot block addresses can be accessed in deep power-down mode).
mobile diskonchip g3 46 data sheet, rev. 1.0 91-sr-011-05-8l 7. t rue ffs t echnology 7.1 general description m-systems? patented trueffs technology was designe d to maximize the benefits of flash memory while overcoming inherent flash li mitations that would otherwise re duce its performance, reliability and lifetime. trueffs emulates a hard disk, making it completely transparent to the os. in addition, since it operates under the os file system layer (see figure 18), it is completely transparent to the application. figure 18: trueffs locati on in system hierarchy trueffs technology support includes: ? binary driver support for all major oss ? trueffs software development kit (trueffs sdk) ? boot software development kit (bdk) ? support for all major cpus, including 8, 16 and 32-bit bus architectures. trueffs technology features: ? block device api ? flash file system management ? bad-block management ? dynamic virtual mapping ? dynamic and static wear-leveling ? power failure management ? implementation of mlc-tailored edc/ecc ? performance optimization ? compatibility with all diskonchip products application os file system trueffs diskonchip
mobile diskonchip g3 47 data sheet, rev. 1.0 91-sr-011-05-8l 7.1.1 built-in operating system support the trueffs driver is integrated into all majo r oss, including symbian, palm os, pocket pc 2002/3, smartphone 2002/3, windows ce/nt, linux (var ious kernels), nucleus, and others. for a complete listing of all available drivers, please refer to m-systems? website, www.m-sys.com . it is advised to use the latest driver versions that can be downloaded from the website. 7.1.2 trueffs software development kit (sdk) the basic trueffs software development kit (sdk) developer guide provides the source code for the trueffs driver. it can be used in an os-less environment or wh en special customization of the driver is required for proprietary oss. when using mobile diskonchip g3 as the boot replacement device, trueffs sdk also incorporates in its source code the boot software that is required fo r this configuration (this package is also available separately). please refer to the diskonchip boot softwar e development kit (bdk) developer guide for further information on using this software package. note: mobile diskonchip g3 is supported by trueffs 6.1 and above. 7.1.3 file management trueffs accesses the flash memory within mobile diskonchip g3 through an 8kb window in the cpu memory space. trueffs provides block device api by using standard file system calls, identical to those used by a mechanical hard disk, to enable reading from and writing to any sector on mobile diskonchip g3. this makes mobile disk onchip g3 compatible with any file system and file system utilities, such as diagnostic tools and applications. when using the flash allocation table (fat) file system, the data stored on mobi le diskonchip g3 uses the fat-16 file system. note: mobile diskonchip g3 is shipped unformatted and contains virgin media. 7.1.4 bad block management since nand flash is an imperfect storage media, it can contain bad blocks th at cannot be used for storage because of their high erro r rates. trueffs automatically de tects and maps out bad blocks upon system initialization, ensuring th at they are not used for storag e. this management process is completely transparent to the user, who is unawa re of the existence and location of bad blocks, while remaining confident of the integrity of data stored. 7.1.5 wear-leveling flash memory can be erased a limited numb er of times. this number is called the erase cycle limit , or write endurance limit , and is defined by the flash array vendor. the erase cycle limit applies to each individual erase block in the flash device. in mobile diskonchip g3, the erase cycle limit of the flash is 100,000 erase cycles. this means th at after approximatel y 100,000 erase cycles, the erase block begins to make storage errors at a ra te significantly higher than the error rate that is typical to the flash. in a typical application, and especi ally if a file system is used, specific pages are constantly updated (e.g., the page/s that contain the fat, registry, etc.). without any special handling, these pages would wear out more rapidly than other pages, reducing the lifetime of the entire flash.
mobile diskonchip g3 48 data sheet, rev. 1.0 91-sr-011-05-8l to overcome this inherent defici ency, trueffs uses m-systems? pate nted wear-leveling algorithm. this wear-leveling algorithm ensures that consecu tive writes of a specific sector are not written physically to the same page in the flash. this sp reads flash media usage evenly across all pages, thereby maximizing flash lifetime. trueffs wear-lev eling extends the flash lifetime 10 to 15 years beyond the lifetime of a typical application. dynamic wear-leveling trueffs uses statistical allocati on to perform dynamic wear-level ing on newly written data. this not only minimizes the number of erase cycles per bl ock, it also minimizes th e total number of erase cycles. because a block erase is the most time- consuming operation, dynamic wear-leveling has a major impact on overall performance. this impact cannot be noticed during th e first write to flash (since there is no need to erase blocks beforehand), but it is more and more noticeable as the flash media becomes full. static wear-leveling areas on the flash media may contain static files, characterized by blocks of data that remain unchanged for very long periods of time, or even for the whole device life time. if wear-leveling were only applied on newly written pages, static areas would ne ver be cycled. this limited application of wear-leve ling would lower life expectancy signif icantly in cases where flash memory contains large static areas. to overcome this problem, trueffs forces data transfer in static areas as well as in dynamic areas, thereby applying wear-leveling to the entire media. 7.1.6 power failure management trueffs uses algorithms based on ?erase after write? in stead of "erase before write" to ensure data integrity during normal operation and in the event of a power failure. used areas are reclaimed for erasing and writing the flash manage ment information into them only after an operation is complete. this procedure serves as a check on data integrity. the ?erase after write? algorithm is also used to update and store mapping information on the flash memory. this keeps the mapping information c oherent even during pow er failures. the only mapping information held in ram is a table poi nting to the location of the actual mapping information. this table is reconstructed during powe r-up or after reset from the information stored in the flash memory. to prevent data from being lost or corr upted, trueffs uses the following mechanisms: ? when writing, copying, or erasing the flash devi ce, the data format remains valid at all intermediate stages. previous data is never er ased until the operation has been completed and the new data has been verified. ? a data sector cannot exist in a partially writte n state. either the operation is successfully completed, in which case the new sector contents are valid, or the operation has not yet been completed or has failed, in which case th e old sector contents remain valid. 7.1.7 error detection/correction trueffs implements a unique mlc-tailored error co rrection code (ecc) algor ithm to ensure data reliability. refer to section 3.7 for furthe r information on the edc/ecc mechanism.
mobile diskonchip g3 49 data sheet, rev. 1.0 91-sr-011-05-8l 7.1.8 special features through i/o control (ioctl) mechanism in addition to standard storage device functi onality, the trueffs driver provides extended functionality. this functi onality goes beyond simple data storag e capabilities to include features such as: formatting the media, read/write protecti on, boot partition(s) access, flash defragmentation and other options. this unique functionality is available in all trueffs- based drivers through the standard i/o control command of the native file system. 7.1.9 compatibility mobile diskonchip g3 requires trueffs driver 6.x or higher. sinc e this driver does not support other diskonchip products, migrating from mob ile diskonchip g3 to any other diskonchip product requires changing the trueffs driver. when using different drivers (e .g. trueffs sdk, bdk, bios extens ion firmware, etc.) to access mobile diskonchip g3, verify that all software is based on the same code base version. it is also important to use only tools (e.g. dformat, dinfo, getimage, etc.) from the same version as the firmware and the trueffs drivers used in th e application. failure to do so may lead to unexpected results, such as lost or corrupted data . the driver and firmware version can be verified by the sign-on messages displayed, or by the versi on information stored in the driver or tool. 7.2 8kb memory window trueffs utilizes an 8kb memory window in the cpu address space, consisting of four 2kb sections as depicted in figure 19. when in reset mode, read cycles from sections 1 and 2 always return the value 00h to create a fixed and know n checksum. when in normal mode, these two sections are used for the internal registers. the 2kb programmable boot block is in section 0 and section 3, to support systems that search for a ch ecksum at the boot stage both from the top and bottom of memory. the addresses de scribed here are relative to the absolute starting address of the 8kb memory window. programmable boot block reset mode flash area window (+ aliases) 000h 800h 1000h 1800h control registers section 0 section 1 section 2 section 3 normal mode 00h programmable boot block programmable boot block 00h programmable boot block figure 19: mobile diskonchip g3 memory map
mobile diskonchip g3 50 data sheet, rev. 1.0 91-sr-011-05-8l 8. r egister d escriptions this section describes various mo bile diskonchip g3 registers a nd their functions, as listed in table 7. most mobile diskonchip g3 registers ar e 8-bit, unless otherwis e denoted as 16-bit. table 7: mobile diskonchip g3 registers address (hex) register name 103e no operation (nop) 1000/1074 chip identification [1:0] 1004 test 1006 bus lock 1008 endian control 100c diskonchip control 1072 diskonchip control confirmation 100a device id select 100e configuration 1010 interrupt control 1020 interrupt status 1014 output control 107c dpd control 1078/107a dma control [1:0] 101c multiburst mode control 8.1 definition of terms the following abbreviations and terms are used within this section: rfu reserved for future use. this bit is u ndefined during a read cycle and ?don?t care? during a write cycle. rfu_0 reserved for future use; when read, this bit always returns the value 0; when written, software should ensure that this bit is always set to 0. rfu_1 reserved for future use; when read, this bit always returns the value 1; when written, software should ensure that this bit is always set to 1. reset value refers to the value immediately present after exiting from reset mode to normal mode. 8.2 reset values all registers return 00h while in reset mode. the re set value written in the register description is the register value after exiting re set mode and entering normal mode . some register contents are undefined at that time (n/a).
mobile diskonchip g3 51 data sheet, rev. 1.0 91-sr-011-05-8l 8.3 no operation (nop) register description: a call to this 16-b it register results in no operati on. to aid in code readability and documentation, software should access th is register when performing cycles intended to create a time delay. address (hex): 103e type: write reset value: none 8.4 chip identification (id) register [0:1] description: these two 16-bit registers are used to identify the diskonchip device residing on the host platform. they always return the same value. address (hex): 1000/1074 type: read only reset value: chip identification register[0]: 0200h chip identification register[1]: fdffh 8.5 test register description: this register enables software to identify multiple mobile diskonchip g3 devices or multiple aliases in the cpus memory space. data written is stored but does not affect the behavior of mobile diskonchip g3. address (hex): 1004 type: read/write reset value: 0 bit no. description 7-0 d[7:0]: data bits
mobile diskonchip g3 52 data sheet, rev. 1.0 91-sr-011-05-8l 8.6 bus lock register description: this register provides a mechan ism for a cpu to request and hold sole access rights to mobile diskonchip g3 in multiprocessor applications. the following algorithm must be implemente d to ensure that only one cpu at a time accesses mobile diskonchip g3: 1. before beginning an indivisible ope ration sequence (e.g. reading/writing a sector to the diskonchip), the value of this register is read. if it is non-zero, then it must continue to be polled until it becomes zero. 2. once the value read is zero, a non-zero value unique to each cpu is written to this register to indicate to ot her cpus that the device is in use. 3. the value written must then be confir med. if the register returns the same value that was written, then the cpu is assured of sole access rights to mobile diskonchip g3. if it is not the same value, then another cpu has claimed access rights to the device and the process must be repeated from step 1. 4. upon completion of the indivisible operat ion sequence, this register must be set to 00h to release the lock and permit other cpus to access the device. address (hex): 1006 type: read/write reset value: 0 bit no. description 7-0 d[7:0]: cpu control value
mobile diskonchip g3 53 data sheet, rev. 1.0 91-sr-011-05-8l 8.7 endian control register description: this 16-bit register is used to control the swapping of the low and high data bytes when reading or writing with a 16-bit host. this provides an endian- independent method of enabling/disa bling the byte swap feature. note: hosts that support 8-bit access only do not need to write to this register. address (hex): 1008 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read/write r r/w description rfu_0 swapl reset value 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 read/write r r/w description rfu_0 swaph reset value 0 0 0 0 0 0 0 0 bit no. description 0 swapl (swap low byte): this bit must be set to enable byte swapping. if the bit is cleared, then byte swapping is disabled. 7-1 reserved for future use. 8 swaph (swap high byte): this bit must be set to enable byte swapping. if the bit is cleared, then byte swapping is disabled. 15-9 reserved for future use.
mobile diskonchip g3 54 data sheet, rev. 1.0 91-sr-011-05-8l 8.8 diskonchip control register /control confirmation register description: these two registers are identical and contain information about the mobile diskonchip g3 operational mode. afte r writing the required value to the diskonchip control register, the compleme nt of that data byte must also be written to the control confirmation regist er. the two writes cycles must not be separated by any other read or write cycles to the mobile diskonchip g3 memory space, except for reads from the programmable boot block space. address (hex): 100c/1072 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read/write r/w r description mode[1:0] mdwren bdet rst_lat rfu_0 reset value 0 0 0 0 1 0 0 0 note: the diskonchip control confirmation register is write only bit no. description 1-0 mode. these bits select the mode of operation, as follows: 00: reset 01: normal 10: deep power-down 2 mdwren (mode write enable). this bit must be set to 1 before changing the mode of operation. it always returns 0 when read. 3 bdet (boot detect). this bit is set w henever the device has entered reset mode as a result of the boot detector triggering. it is cleared by writing a 1 to this bit. 4 rst_lat (reset latch). this bit is set wh enever the device has entered the reset mode as a result of the rstin# input signal be ing asserted or the internal voltage detector triggering. it is cleared by writing a 1 to this bit. 7-5 reserved for future use.
mobile diskonchip g3 55 data sheet, rev. 1.0 91-sr-011-05-8l 8.9 device id select register description: in a cascaded configuration, this register controls whic h device provides the register space. the value of bits id[0:1 ] is compared to the value of the id configuration input pins/balls. the devi ce whose id input matches the value of bits id[0:1] responds to read and write cycles. address (hex): 100a bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read/write r r/w description rfu_0 id[1:0] reset value 0 0 0 0 0 0 0 0 bit no. description 1-0 id[1:0] (identification). the device whose id i nput pins/balls match the value of bits id[0:1] responds to read and write cycles to register space. 7-2 reserved for future use. 8.10 configuration register description: this register i ndicates the current configurati on of mobile diskonchip g3. unless otherwise noted, the bits are rese t only by a hardware reset, and not upon boot detection or any other entry to reset mode. address (hex): 100e bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read/write r r/w r description if_cfg rfu_0 max_id rfu rfu_0 vccq_3v reset value x 0 0 0 0 0 0 x bit no. description 0 vccq_3v: reflects the level of vccq input. 0: vccq < 2.0v 1: vccq > 2.5v 6, 3-1 reserved for future use. 5-4 max_id (maximum device id). this fiel d controls the programmable boot block address mapping when multiple devices are used in a cascaded configuration, using the id[1:0] inputs. it should be programmed to the highest id value that is found by software in order to map all available boot blocks into usable address spaces. 7 if_cfg (interface configuration). reflec ts the state of the if_cfg input pin.
mobile diskonchip g3 56 data sheet, rev. 1.0 91-sr-011-05-8l 8.11 interrupt control register description: this 16-bit register controls how interrupts are generate d by mobile diskonchip g3, and indicates which of the following fi ve sources has asserted an interrupt: 0: flash array is ready 1: data protection violation 2: reading or writing more flash data th an was specified in the dcnt field of ecc control register[0] 3: bch ecc error detected (this feature is provided to support multi-page dma transfers) 4: real-time clock 5: completion of a dma operation address (hex): 1010 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read/write r r/w description rfu_0 enable reset value 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 read/write r/w description gmask edge mask reset value 0 0 0 0 0 0 0 0 bit no. description 5-0 enable. for each bit in this field: 1: enables the respective bit in the status fi eld of the interrupt status register to latch activity and cause an interrupt if the corresponding mask bit is set. 0: holds the respective bit in the status fi eld in the cleared state. to clear a pending interrupt and re-enable further interrupts on that channel, the respective enable bit must be cleared and then set. 7-6 reserved for future use. 13-8 mask. for each bit in this field: 1: enables the respective bit in the status fi eld of the interrupt stat us register to generate an interrupt by asserting the irq# output. 0: prevents the respective status bit from generating an interrupt.
mobile diskonchip g3 57 data sheet, rev. 1.0 91-sr-011-05-8l bit no. description 14 edge. selects edge or level triggered interrupts: 0: specifies level-sensitive interrupts in wh ich the irq# output remains asserted until the interrupt is cleared. 1: specifies edge-sensitive in terrupts in which the irq# output pulses low and return to logic 1. 15 gmask (global mask). 1: enables the irq# output to be asserted. setting this bit while one or more interrupts are pending will generate an interrupt. 0: forces the irq# output to the negated state. 8.12 interrupt status register description: this register indicates whic h interrupt source created an interrupt. address (hex): 1020 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read/write r r/w description rfu_0 status reset value 0 0 0 0 0 0 0 0 bit no. description 5-0 status. indicates which of the following interrupt sources created an interrupt: 0: flash array is ready 1: data protection violation 2: reading or writing more flash data than wa s specified in the dcnt field of ecc control register[0] 3: bch ecc error detected (this feature is pr ovided to support multi-page dma transfers) 4: real time clock 5: completion of a dma operation 7-6 reserved for future use.
mobile diskonchip g3 58 data sheet, rev. 1.0 91-sr-011-05-8l 8.13 output control register description: this register contro ls the behavior of certain output signals. this register is reset by a hardware reset, not by entering reset mode. note: when multiple devices are cascaded, wr iting to this register will affect all devices regardless of the value of the id[1:0] inputs. address (hex): 1014 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read/write r r/w description rfu_0 turbo pu_dis busy_en reset value 0 0 0 0 0 0 0 1 bit no. description 0 busy_en (busy enable). controls the asse rtion of the busy# output during a download initiated by a soft reset. 1: enables the assertion of the busy# output 0: disables the assertion of the busy# output upon the assertion of the rstin# input, th is bit will be set automatically and the busy# output signal will be asserted until the co mpletion of the download process. 1 pu_dis (pull-up disable). controls t he pull-up resistors d[15:8] as follows: 1: always disable the pull-ups 0: enable the pull-ups when if_cfg = 0 2 turbo. activates turbo operation. 0: diskonchip is used in normal operation, without improved access time. output buffers are enabled only after a long enough delay to guarantee that there will be no more than a single transition on each bit. 1. diskonchip is used in turbo operation. ou tput buffers are enabled immediately after the assertion of oe# and ce#, resulting in im proved access time. read cycles from the programmable boot block may result in additional noise and power dissipation due to multiple transitions on the data bus. 7-3 reserved for future use.
mobile diskonchip g3 59 data sheet, rev. 1.0 91-sr-011-05-8l 8.14 dpd control register description: this register specifies the behavior of the dpd input signal. address (hex): 107c bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read/write r r/w description pd_ok rfu_0 mode[0:3] reset value 0 0 0 0 0 0 0 0 bit no. description 3-0 mode[0:3]. controls the behavior of the dpd input: 0000: dpd input is not used to control dpd mode 0001: dpd mode exited on rising edge of dpd input 0010: dpd mode exited on falling edge of dpd input 0100: dpd mode is entered when dpd=1 and exited when dpd=0 1000: dpd mode is entered when dpd=0 and exited when dpd=1 6-4 reserved for future use. 7 pd_ok (power- down ok). this read-only bit i ndicates that it is currently possible to put mobile diskonchip g3 in deep power-down mode.
mobile diskonchip g3 60 data sheet, rev. 1.0 91-sr-011-05-8l 8.15 dma control register [1:0] description: these two 16-bit registers sp ecify the behavior of the dma operation. address (hex): 1078/107a bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read/write r r/w description rfu_0 sector_count reset value 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 read/write r r/w r description dma_en pause edge polrty rfu_0 reset value 0 0 0 0 0 0 0 0 bit no. description 6-0 sector_count. specifies the number of 512 -byte sectors to be transferred plus one. writing a v (a value of 0) indicates a transfer of one sector. reading a value of 0 indicates that there is still one sector to be transferre d). this field is decremented by mobile diskonchip g3 after reading the ecc checksum from each sector. in the event of an ecc error, this field indicates the number of sectors remaining to be transferred. 11-7 reserved for future use. 12 polrty (polarity). specifies the polarity of the dmarq# output: 0: dmarq# is normally logic -1 and falls to initiate dma 1: dmarq# is normally logic -0 and rises to initiate dma 13 edge. controls the behavior of the dmarq# output: 1: dmarq# pulses to the asserted state for 250 ns (typical) to initiate the block transfer. 0: dmarq# switches to the active state to initiate the block transfer and returns to the negated state at the beginning of the cycle in which the dcnt field of the ecc control register[0] reaches the value specified by the negate_count field of the dma control register[1]. 14 pause. this bit is set in the event of an ecc error during a dma operation. after reading the ecc parity registers and correcting the errors, the software must clear this bit to resume the dma operation. 15 dma_en (dma enable). setting this bit enables dma operation.
mobile diskonchip g3 61 data sheet, rev. 1.0 91-sr-011-05-8l dma control register [1] bits 15-10 bits 9-0 read/write r r/w description rfu_0 negate_count reset value 0 0 0 0 0 0 0 0 bit no. description 9-0 negate_count. when the edge bit of dma c ontrol register[0] is a 0, this bit must be programmed to specify the bus cycle in wh ich dmarq# will be negated as follows: negate_count = bytes_remainin g + 16 + bytes_per_cycle. example: to negate dmarq# at the beginning of the cycle in which the last word is to be transferred by a 16-bit host: negate_count = 2 + 16 + 2 = 20. 15-10 reserved for future use.
mobile diskonchip g3 62 data sheet, rev. 1.0 91-sr-011-05-8l 8.16 multiburst mode control register description: this 16-bit register controls th e behavior of mobile diskonchip g3 during multiburst mode read cycles. address (hex): 101c bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read/write r r/w description rfu_0 hold clk_inv bst_en reset value 0 0 0 0 0 0 0 0 bit 15 bit 14 bit 13 12 bi t 11 bit 10 bit 9 bit 8 read/write r/w description length latency reset value 0 0 0 0 0 0 0 0 bit no. description 0 bst_en (multiburst mode enable). e nables multiburst mode read cycles. 0: the clk input is disabled and may be left floating. burst read cycl es are not supported. 1: the clk input is enabled. subsequent read cycles must be multiburst mode. 1 clk_inv (clock invert). selects the edge of the clk input on which ce# and oe# are sampled. 0: ce# and oe# are sampled on the rising edge of clk. 1: ce# and oe# are sampled on the falling edge of clk, and there will be an additional ? clock delay from ce#/oe# asserted until the first data word may be latched on d[15:0]. 2 hold. specifies if the data output on d[15:0] during multiburst mode read cycles should be held for an additional clock cycle. 0: data on the d[15:0] outputs is held for one clock cycle 1: data on the d[15:0] outputs is held for two clock cycles 3-7 reserved for future use. 8-11 latency. controls the number of clock cycles between when mobile diskonchip g3 samples oe# and ce# asserted and the first word of data is available to be latched by the host. this number of clock cycles is equal to 2 + latecncy. if hold = 1, then the data is available to be latched on this clock and on the subsequent clock. 12-15 length. specifies the number of byte/wor ds (depending on if_cfg) to be transferred in each burst cycle: hold=0: number of bytes/words = 2 ^ length hold=1: number of bytes/words = 2 ^ (length ? 1) note: the maximum value of length is 10.
mobile diskonchip g3 63 data sheet, rev. 1.0 91-sr-011-05-8l 9. b ooting from m obile d isk o n c hip g3 9.1 introduction mobile diskonchip g3 can function both as a flas h disk and as the system boot device. mobile diskonchip g3 default firmware contains drivers to enable it to perform as the os boot device under dos (see section 9.2). for other oss, please refe r to the readme file of the trueffs driver. if mobile diskonchip g3 is configured as a flash disk and as the system b oot device, it contains the boot loader, an os image and a file system. in such a configuration, mobile diskonchip g3 can serve as the only non-volatil e device on board. refer to secti on 9.3.2 for further information on boot replacement. 9.2 boot procedure in pc-compatible platforms when used in pc-compatible platforms, mobile diskonchip g3 is connected to an 8kb memory window in the bios expansion memory range, typically located betw een 0c8000h to 0effffh. during the boot process, the bios loads the true ffs firmware into the pc memory and installs mobile diskonchip g3 as a disk drive in the sy stem. when the operating system is loaded, mobile diskonchip g3 is recognized as a standard disk. no external software is required to boot from mobile diskonchip g3. figure 20 illustrates the location of the mobile di skonchip g3 memory window in the pc memory map. 8k 1m 640k 0 display ram 0c8000h bios 0b0000h 0f0000h 0fffffh diskonchip extended memory figure 20: mobile diskonchip g3 memory window in pc memory map after reset, the bios code first executes the powe r on self-test (post) and then searches for all expansion rom devices. when mobile diskonchip g3 is located, the bios code executes from it the ipl code, located in the xip portion of the programmable boot block. this code loads the trueffs driver into system memory , installs mobile diskonchip g3 as a disk in the system, and then returns control to the bi os code. the operating system subsequently identifies mobile diskonchip g3 as an available disk. trueffs responds by emulating a hard disk. from this point onward, mobile diskonchip g3 app ears as a standard disk drive. it is assigned a drive letter and can be used by a ny application, without any modificati ons to either the bios set-up
mobile diskonchip g3 64 data sheet, rev. 1.0 91-sr-011-05-8l or the autoexec.bat/config.sys file s. mobile diskonchip g3 can be used as the only disk in the system, with or without a floppy drive, and with or without hard disks. the drive letter assigned depends on how mobile diskonchip g3 is used in the system, as follows: ? if mobile diskonchip g3 is used as the only di sk in the system, the system boots directly from it and assigns it drive c. ? if mobile diskonchip g3 is used with other disks in the system: o mobile diskonchip g3 can be configured as the last drive (the default configuration). the system assigns drive c to the hard disk and drive d to mobile diskonchip g3. o alternatively, mobile diskonchip g3 can be configured as the syst em?s first drive. the system assigns drive d to the hard disk and drive c to mobile diskonchip g3. if mobile diskonchip g3 is used as the os boot device when configured as drive c, it must be formatted as a bootable device by copying the os files onto it. this is done by using the sys command when running dos. 9.3 boot replacement 9.3.1 pc architectures in current pc architectures, the first cpu fetch (aft er reset is negated) is mapped to the boot device area, also known as the reset vector . the reset vector in pc architectures is located at address ffff0, by using a jump command to the beginning of the bios chip (usually f0000 or e0000). the cpu executes the bios code, initializes th e hardware and loads mobile diskonchip g3 software using the bios expansion search routin e (e.g. d0000). refer to section 9.2 for a detailed explanation on the boot sequence in pc-compatible platforms. mobile diskonchip g3 implements both disk and boot functions when it re places the bios chip. to enable this, mobile diskonchip g3 requi res a location at two different addresses: ? after power-up, mobile diskonchip g3 must be mapped in f segment, so that the cpu fetches the reset vector from address ffff0, where mobile diskonchip g3 is located. ? after the bios code is loaded into ram and st arts execution, mobile diskonchip g3 must be reconfigured to be located in the bios expans ion search area (e.g. d0000) so it can load the trueffs software. this means that the cs# signal must be remappe d between two different addresses. for further information on how to achieve this, refer to application note ap-doc-047, designing diskonchip as a flash disk and boot device replacement .
mobile diskonchip g3 65 data sheet, rev. 1.0 91-sr-011-05-8l 9.3.2 non-pc architectures in non-pc architectures, the boot code is executed from a boot rom, and the drivers are usually loaded from the storage device. when using mobile diskonchip g3 as the sy stem boot device, the cpu fetches the first instructions from the mobile diskonchip g3 pr ogrammable boot block, which contains the ipl. since in most cases this block cannot hold the entire boot loader, the ipl runs minimum initialization, after which the secondary program loader (spl) is copied to ram from flash. the remainder of the boot loader code then runs from ram. the ipl and spl are located in a separate (binary) partition on mobile diskonchip g3, and can be hardware protected if required. . 9.3.3 asynchronous boot mode platforms that host cpus that wake up in mult iburst mode should use asynchronous boot mode when using mobile diskonchip g3 as the system boot device. during platform initialization, certain cpus wake up in 32-bit mode and issue instruction fetch cycles continuously. an xscale cpu, for example, in itiates a 16-bit read cycl e, but afte r the first word is read, it continues to hold ce# and oe# a sserted while it increments the address and reads additional data as a burst. a st rongarm cpu wakes up in 32-bit mode and issues double-word instruction fetch cycles. since mobile diskonchip g3 derives its internal clock signal from the ce#, oe# and we# inputs, it cannot distinguish between these burst cycles. to support this type of access, mobile diskonchip g3 must be set in asynchronous boot mode by setting the ram mode select byte to 8fh. this can be done through the mobile diskonchip g3 format utility or by customizing the ipl code. for more information on the format utility, refer to the diskonchip software utilities user manual or the trueffs software development kit (sdk) developer guide. once in asynchronous boot mode, the cpu can fetch its instruction cycles from the mobile diskonchip g3 programmable bo ot block. after reading from this block and completing boot, mobile diskonchip g3 returns to derive its in ternal clock signal from the ce#, oe# and we# inputs. please refer to secti on 11.3 for read timing specifications for asynchronous boot mode.
mobile diskonchip g3 66 data sheet, rev. 1.0 91-sr-011-05-8l 10. d esign c onsiderations 10.1 general guidelines a typical risc processor memory architecture is shown in figure 21. it may include the following devices: ? mobile diskonchip g3 : contains the os image, applicatio ns, registry entries, back-up data, user files and data, etc. it can also be used to perform boot operation, thereby replacing the need for a separate boot device. ? cpu : mobile diskonchip g3 is compatible with all major cpus in the mobile market, including: o arm-based cpus o texas instruments omap o intel strongarm sa-1100/1 and xscale o superh sh-3/4 o motorola powerpc mpc8xx and dragonball mx1 o philips pr31700 o nec vrseries vr3/4xxxx ? boot device : rom or nor flash that contains the boot code required for system initialization, kernel relocation, loading the ope rating systems and/or other app lications and files into the ram and executing them. ? ram/dram memory : this memory is used for code execution. ? other devices : a dsp processor, for example, may be used in a risc architecture for enhanced multimedia support. mobile diskonchip g3 boot rom or nor fl h boot device * cpu ram/dram other devices when used as a boot device, mobile diskonchip g3 el iminates the need for a dedicated boot rom/nor device. figure 21: typical system architecture using mobile diskonchip g3
mobile diskonchip g3 67 data sheet, rev. 1.0 91-sr-011-05-8l 10.2 standard nor-like interface mobile diskonchip g3 uses a nor-like inte rface that can easily be connected to any microprocessor bus. with a standa rd interface, it requires 13 addre ss lines, 8 data lines and basic memory control signals (ce#, oe#, we#), as shown in figure 22 below. typically, mobile diskonchip g3 can be mapped to any free 8kb memory space. in a pc-compatible platform, it is usually mapped into the bios expansion area. if th e allocated memory window is larger than 8kb, an automatic anti-aliasing mechanism prevents th e firmware from being loaded more than once during the rom expansion search. mobile diskonchip g3 address* data output enable write enable chip enable reset chip id vss 3.3 v busy# 10 nf 0.1 uf vcc vccq d[15:0] oe# we# ce# rstin# id[1:0] a[12:0] 10 nf 0.1 uf 1.8v or 3.3v lock# clk irq# dmarq# dpd 1-20 kohm (*) address a0 is multiplexed with the dpd signal. figure 22: standard system interface notes: 1. the 0.1 f and the 10 nf low-inductance high-frequency capacitors must be attached to each of the device?s vcc and vss pins/balls. these capacitors must be placed as close as possible to the package leads. 2. mobile diskonchip g3 is an edge-sen sitive device. ce#, oe # and we# should be properly terminated (according to board layout, serial paralle l or both terminations) to avoid signal ringing.
mobile diskonchip g3 68 data sheet, rev. 1.0 91-sr-011-05-8l 10.3 multiplexed interface with a multiplexed interface, mobile diskonchip g3 requires the signals shown in figure 23 below. mobile diskonchip g3 address/data avd# output enable write enable chip enable reset chip id vss 3.3 v busy# 10 nf 0.1 uf vcc vccq avd# oe# we# ce# rstin# id0 ad[15:0] 10 nf 0.1 uf 1.8v or 3.3v lock# dmarq# clk irq# dpd 1-20 kohm figure 23: multiplexed system interface 10.4 connecting control signals 10.4.1 standard interface when using a standard nor-like interface, connect the control signals as follows: ? a[12:0] ? connect these signals to the host?s address signals (see section 10.8 for platform-related considerations). address signal a[0] is multiplexed with the dpd signal. ? d[15:0] ? connect these signals to the host?s data signals (see section 10.8 for platform-related considerations). ? output enable (oe#) and write enable (we#) ? connect these signals to the host rd# and wr# signals, respectively. ? chip enable (ce#) ? connect this signal to the memory address decoder. most risc processors include a programmable decoder to generate various chip select (cs) outputs for different memory zones. these cs signals can be programmed to support different wait states to accommodate mobile diskonchip g3 timing specifications. ? power-on reset in (rstin#) ? connect this signal to the host active-low power-on reset signal.
mobile diskonchip g 3 69 data sheet, rev. 1.0 91-sr-011-05-8l ? chip identification (id[1:0]) ? connect these si gnals as shown in figure 22. both signals must be connected to vss if the host uses only one diskonchip. if more than one device is being used, refer to section 10.6 for more information on device cascading. ? busy (busy#) ? this signal indicates when the de vice is ready for first access after reset. it may be connected to an input port of the host, or alternatively it may be used to hold the host in a wait-state condition. the later op tion is required for hosts that boot from mobile diskonchip g3. ? dmarq# (dma request) ? output used to control multi-page dma operations. connect this output to the dma controlle r of the host platform. ? irq# (interrupt request) ? connect this signal to the host interrupt. ? lock (lock#) ? connect to a logical 0 to prevent the usage of the protection key to open a protected partition. connect to logical 1 in order to enable usage of protection keys. ? deep-power down (dpd) ? multiplexed with a[0]. ? 8/16 bit interface configur ation (if_cfg) ? this signal is required for configuring the device for 8- or 16-bit access mode. when negated, th e device is configured for 8-bit access mode. when asserted, 16-bit access mode is operative. ? clock (clk) ? this input is used to support mu ltiburst operation when reading flash data. refer to section 4.1 for further information on multiburst operation. 10.4.2 multiplexed interface mobile diskonchip g3 can use a multiplexed interface to connect to the multiplexed bus (asynchronous read/write protocol ). in this configuration, the id [1] input is driven by the host's avd# signal, and the d[15:0] pins/balls, used for both address inputs and data , are connected to the host ad[15:0] bus. as with a standard interface, only address bits [12:0] are significant. this mode is automatically entered when a falling e dge is detected on id[1]. this edge must occur after rstin# is negated and before oe# and ce# are both as serted; i.e., the first read cycle made to diskonchip must observe the multiplexed mode pr otocol. see section 11.3 for more information about the related timing requirements. please refer to section 2.4 fo r pinout and signal descriptions and to section 11.3 for timing specifications for a multiplexed interface.
mobile diskonchip g 3 70 data sheet, rev. 1.0 91-sr-011-05-8l 10.5 implementing the interrupt mechanism 10.5.1 hardware configuration to configure the hardware for working with the in terrupt mechanism, connect the irq# pin/ball to the host interrupt input. note: a nominal 10 k ? pull-up resistor must be c onnected to this pin/ball. 10.5.2 software configuration configuring the software to support the irq# interrupt is performed in two stages. stage 1 configure the software so that when the syst em is initialized, the following steps occur: 1. the correct value is written to the interrupt co ntrol register to confi gure mobile diskonchip g3 for: ? interrupt source: flash ready, data protection, last byte during dma has been transferred, or bch ecc error has been detected (used during multi-page dma operations). ? output sensitivity: either edge or level-triggered note: refer to section 8 for further informa tion on the value to write to this register. 2. the host interrupt is configured to the selected input sensitivity, either edge or level-triggered. 3. the handshake mechanism between the inte rrupt handler and the os is initialized. 4. the interrupt service rou tine to the host interrupt is connected and enabled. stage 2 configure the software so that for every l ong flash i/o operation, the following steps occur: 1. the correct value is written to the interrupt control register to enable the irq# interrupt. note: refer to section 8 for further informa tion on the value to write to this register. 2. the flash i/o operation starts. 3. control is returned to the os to continue ot her tasks. when the irq# interrupt is received, other interrupts are disabled and the os is flagged. 4. the os either returns control immediately to the trueffs dr iver, or waits for the appropriate condition to return contro l to the trueffs driver.
mobile diskonchip g 3 71 data sheet, rev. 1.0 91-sr-011-05-8l 10.6 device cascading when connecting mobile diskonchip g3 512mb using a standard interface, up to four devices can be cascaded with no external deco ding circuitry. figure 24 illustrates the configuration required to cascade four devices on the host bu s (only the relevant cascading signals are included in this figure, although all other signals must also be connected). all pins/balls of the cascaded devices must be wired in common, except for id0 and id1. the id input pins/balls are strapped to vcc or vss, according to the location of each di skonchip. the id pin/ba ll values determine the identity of each device. for example, the first device is identified by connecting the id pins/balls as 00, and the last device by connecting the id pins/balls as 11. sy stems that use only one mobile diskonchip g3 512mb must connect the id pins/balls as 00. additional devices must be configured consecutively as 01, 10 and 11. when mobile diskonchip g3 512 mb uses a multip lexed interface, the valu e of id[1] is set to logic 0. therefore, only two devices can be cascaded using id[0]. mobile diskonchip 1gb device cannot be cascaded when using a multiplexed interface. id0 id1 ce# oe# we# ce# we# oe# vss vss id0 id1 ce# oe# we# vss vcc 2nd id0 id1 ce# oe# we# vcc vss 3rd id0 id1 ce# oe# we# vcc vcc 4th 1st figure 24: standard interface, cascaded configuration note: when more than one mobile diskonchip g3 is cascaded, a boot block of 4kb is available. the programmable boot block of each device is mapped to a unique address space.
mobile diskonchip g 3 72 data sheet, rev. 1.0 91-sr-011-05-8l 10.7 boot replacement a typical risc architecture uses a boot rom fo r system initialization. the boot rom is also required to access mobile diskonchip g3 during th e boot sequence in order to load os images and the device drivers. m-systems? boot software development kit (bdk) and dos utilities enable full control of mobile diskonchip g3 during the boot sequence. for a comp lete description of thes e products, refer to the diskonchip boot software development kit (bdk) developer guide and the diskonchip software utilities user manual. these tools enable the following operations: ? formatting mobile diskonchip g3 ? creating multiple partitions for different storage needs (os images files, register entry files, back-up partitions, and fat/nftl partition) ? loading the os image file figure 25 illustrates the system boot flow using mobile diskonchip g3 in a risc architecture. boot loader os image binary partition (os image storage) flash disk partition (file storage) power-up ram basic system initialization boot loader copies os image to ram os start-up code mobile diskonchip g3 copy image to ram take image from diskonchip g3 figure 25: system boot flow with mobile diskonchip g3
mobile diskonchip g 3 73 data sheet, rev. 1.0 91-sr-011-05-8l 10.8 platform-specific issues following is a description of hardware design issues for major embedded risc processor families. 10.8.1 wait state wait states can be implemented only when mobile diskonchip g3 is designed in a bus that supports a wait state insertion, and supplies a wait signal. 10.8.2 big and little endian systems mobile diskonchip g3 is a littl e endian device. therefore, byte lane 0 (d[7:0]) is its least significant byte (lsb) and byte lane 1 (d[15:8]) is its most significant byte (msb). within the byte lanes, bit d0 and bit d8 are the least signifi cant bits of their resp ective byte lanes. mobile diskonchip g3 can be connected to a bi g endian device in one of two ways: 1. make sure to identify byte lane 0 and byte lane 1 of your processor. th en, connect the data bus so that the byte lanes of the cpu match the by te lanes of mobile disk onchip g3. pay special attention to processors that also change the bit ordering wi thin the bytes (for example, powerpc). failing to follow these rules results in improper connection of mobile diskonchip g3, and prevents the trueffs driver from identifying it. 2. set the bits swaph and swapl in the endian control register. this enables byte swapping when used with 16-bit hosts. 10.8.3 busy signal the busy signal (busy#) indicates that mobile diskonchip g3 has not yet completed internal initialization. after reset, busy# is asserted wh ile the ipl is downloaded into the internal boot block and the data protection structures (dps) are downloaded to the protection state machines. once the download process is completed, busy# is ne gated. it can be used to delay the first access to mobile diskonchip g3 until it is ready to accept valid cycles. note: the trueffs driver does not use this signal to indicate that the flash is in busy state (e.g. program, read, or erase). 10.8.4 working with 8/16/32-bit systems mobile diskonchip g3 uses a 16-bit data bus an d supports 16-bit data access by default. however, it can be configured to support 8 or 32-bit data ac cess mode. this section describes the connections required for each mode. the default of the trueffs driver for mobile diskonch ip g3 is set to work in 16-bit mode. it must be specially configured to support 8 and 32-bit mode. please see trueffs documentation for further details. note: the diskonchip data bus must be connected to the least significant bits (lsb) of the system. the system engineer must verify wh ether the matching host signals are sd[7:0], sd[15:8] or d[31:24].
mobile diskonchip g 3 74 data sheet, rev. 1.0 91-sr-011-05-8l 8-bit (byte) data access mode when configured for 8-bit operati on, pin/ball if_cfg should be connected to vss, and data lines d[15:8] are internally pulled up and may be left unconnected. the controller routes odd and even address accesses to the appropriate by te lane of the flash and ram. host address sa0 must be connecte d to mobile diskonchip g3 a0, sa 1 must be connected to a1, etc. 16-bit (word) data access mode to set mobile diskonchip g3 to work in 16-b it mode, the if_cfg pin/ball must be connected to vcc. in 16-bit mode, the programmable boot block is accessed as a true 16-bit device. it responds with the appropriate data when the cpu issues either an 8-bit or 16-bit read cycle. the flash area is accessed as a 16/32-bit device, regardless of the interface bus width. this has no affect on the design of the interface between mo bile diskonchip g3 and the host. the trueffs driver handles all issues regarding moving data in and out of mobile diskonchip g3. see table 8 for a0 and if_cfg settings for vari ous functionalities with 8/16-bit data access. table 8: active data bus lines in 8/16-bit configuration a0 if_cfg functionality 0 1 16-bit access through both buses 0 0 8-bit access to even bytes through low 8-bit bus 1 0 8-bit access to odd bytes through low 8-bit bus 1 1 illegal 32-bit (double word) data access mode in a 32-bit bus system that cannot execute byte or word aligned accesses, the system address lines sa0 and sa1 are always 0. consecutive double wo rds (32-bit words) are differentiated by sa2 toggling. therefore, in 32-bit systems that s upport only 32-bit data access cycles, mobile diskonchip g3 signal a0 is connected to vss and a1 is connected to the first system address bit that toggles; i.e., sa2. system host sa13 sa12 sa11 sa10 sa9 sa8 sa7 sa6 sa5 sa4 sa3 sa2 sa1 sa0 a12a11a10a9 a8a7a6a5a4a3a2a1a0 mobile diskonchip g3 note: the prefix ?s? indicates system host address lines figure 26: address shift configurat ion for 32-bit data access mode
mobile diskonchip g 3 75 data sheet, rev. 1.0 91-sr-011-05-8l 10.9 design environment mobile diskonchip g3 provides a comple te design environment consisting of: ? evaluation boards (evbs) for enabling software integration and development with mobile diskonchip g3, even before the target platform is available. ? programming solutions: o gang programmer o programming house o on-board programming ? trueffs software development kit (sdk) a nd boot software development kit (bdk) ? dos utilities: o dformat o getimage/putimage o dinfo ? documentation: o data sheet o application notes o technical notes o articles o white papers please visit the m-systems website ( www.m-sys.com ) for the most updated documentation, utilities and drivers.
mobile diskonchip g 3 76 data sheet, rev. 1.0 91-sr-011-05-8l 11. p roduct s pecifications 11.1 environmental specifications 11.1.1 operating temperature commercial temperatur e range: 0c to +70c extended temperature range: -40c to +85c 11.1.2 thermal characteristics table 9: thermal characteristics thermal resistance ( c/w) junction to case ( jc ): 30 junction to ambient ( ja ): 85 11.1.3 humidity 10% to 90% relative, non-condensing 11.1.4 endurance mobile diskonchip g3 is based on nand mlc flash technology, which guarantees a minimum of 100,000 erase cycles. due to the trueffs wear-leveli ng algorithm, the life span of all diskonchip products is significantly prol onged. m-systems? website ( www.m-sys.com ) provides an online life- span calculator to facilitate applic ation-specific endurance calculations. 11.2 electrical specifications 11.2.1 absolute maximum ratings table 10: absolute maximum ratings symbol parameter rating1 unit vcc dc core supply voltage -0.6 to 4.6 v vccq dc i/o supply voltage -0.6 to 4.6 v t 1supply maximum duration of applying vccq without vcc, or vcc without vccq 1000 mse c i in input pin/ball current (25 c) -10 to 10 ma v in 2 input pin/ball voltage -0.6 to vccq+0.3v, 4.6v max v t stg storage temperature -55 to 150 c esd: charged device model esd cdm 1000 v esd: human body model esd hbm 2000 v 1. permanent device damage may occur if absolute maximum ratings are exceeded. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. the voltage on any ball may undershoot to -2.0 v or overshoot to 6.6v for less than 20 ns. 3. when operating mobile diskonchip g3 with separate power supplies for vcc and v ccq, it is recommended to turn both supplies on and off simultaneously. providing power sepa rately (either at power-on or power-off) can cause exce ssive power dissipation. da mage to the device may result if this condition persists for more than 1 second.
mobile diskonchip g 3 77 data sheet, rev. 1.0 91-sr-011-05-8l 11.2.2 capacitance table 11: capacitance symbol parameter conditions min typ max unit input capacitance (512mb device) tbd 10 pf c in input capacitance (1gb device) v in = 0v tbd 20 pf output capacitance (512mb device) tbd 10 pf c out output capacitance (1gb device) v o = 0v tbd 20 pf capacitance is not 100% tested. 11.2.3 dc electrical characteristics over operating range see table 12 and table 13 for dc characteri stics for vccq ranges 1.65-2.0v and 2.5-3.6v i/o, respectively. table 12: dc characteristics, vccq = 1.65-2.0v i/o symbol parameter conditions min typ max unit vcc core supply voltage 2.5 3.0 3.6 v vccq input/output supply voltage 1.65 1.8 2.00 v v ih high-level input voltage vccq ? 0.4 v v il low-level input voltage 0.4 v v oh high-level output voltage i oh = -100 a vccq ? 0.1 v d[15:0] i ol = 100 a 0.1 v v ol low-level output voltage irq#, busy#, dmarq# 4ma 0.3 v input leakage current 2 (512mb device) 10 a i ilk input leakage current 2 (1gb device) 20 a output leakage current (512mb device) 10 a i iolk output leakage current (1gb device) 20 a i cc active supply current 1 , vcc pin/ball cycle time = 100 ns 10 45 ma standby supply current, vcc pin/ball (512mb device) deep power-down mode3 10 40 a i ccs standby supply current, vcc pin/ball (1gb device) deep power-down mode3 20 80 a 1. vcc = 3v, vccq = 1.8v, outputs open 2. the ce# input includes a pull-up resistor wh ich sources 0.3~1.4 (tbd) ua at vin=0v 3. deep power-down mode is achieved by a sserting rstin# (when in normal mode) or writing the proper wr ite sequence to the diskonchip registers, and asserting the ce# input = vccq.
mobile diskonchip g 3 78 data sheet, rev. 1.0 91-sr-011-05-8l table 13: dc characteristics, vccq = 2.5v-3.6v symbol parameter conditions min typ max unit vcc core supply voltage 2.5 3.3 3.6 v vccq input/output supply voltage 2.5 3.3 3.6 v v ih high-level input voltage 2.1 v v il low-level input voltage 0.7 v 3.0v < vccq < 3.6v -4 ma i ohmax maximum high level output current 2.5v < vccq < 3.0v -4 ma 3.0v < vccq < 3.6v 8 ma i olmax maximum low-level output current 2.5v < vccq < 3.0v 5 ma input leakage current 2 (512mb device) 10 a i ilk input leakage current 2 (1gb device) 20 a output leakage current (512mb device) 10 a i iolk output leakage current (1gb device) 20 a i oh = i ohmax 2.5v < vccq < 2.7v vccq- 0.3 v oh high-level output voltage i oh = i ohmax 2.5v < vccq < 3.6v 2.4 v v ol low-level output voltage i ol= i olmax 0.4 v i cc active supply current, vcc+vccq pins/balls 1 cycle time = 100 ns 10 45 ma standby supply current, vcc+vccq pins/balls (512mb single-die device) deep power-down mode 3 10 40 a i ccs standby supply current, vcc+vccq pins/balls (1gb dual-die device) deep power-down mode 3 20 80 a 1. vcc = vccq = 3.3v, outputs open 2. the ce# input includes a pull-up resistor which sources 0.3~1.4 (tbd) a at vin=0v 3. deep power-down mode is achieved by a sserting rstin# (when in normal mode) or writing the proper wr ite sequence to the diskonchip registers, and asserting the ce# input = vccq.
mobile diskonchip g 3 79 data sheet, rev. 1.0 91-sr-011-05-8l 11.2.4 ac operating conditions timing specifications are based on the conditions defined below. table 14: ac characteristics parameter vccq = 1.65-2.0v vccq = 2.5-3.6v ambient temperature (ta) -40c to +85c -40c to +85c core supply voltage (vcc) 2.5v to 3.6v 2.5v to 3.6v input pulse levels 0.2/vccq-0.2v 0v/2.5v input rise and fall times 3 ns 3 ns input timing levels 0.9v 1.5v output timing levels 0.9v 1.5v output load 30 pf 100 pf
mobile diskonchip g 3 80 data sheet, rev. 1.0 91-sr-011-05-8l 11.3 timing specifications 11.3.1 read cycle timing standard interface ce# a[12:0] t rec (oe) t ho (ce1) t su (ce0) t su (ce1) t ho (ce0) t hiz (d) t acc t loz (d) t ho (a) t su (a) oe# d[15:0] we# t p (oe fre0) figure 27: standard interface, read cycle timing ce# a[12:0] t rec (oe) t ho (ce1) t su (ce0) t su (ce1) t ho (ce0) t hiz (d) t acc t loz (d) t ho (a) t su (a) oe# d[15:0] we# t acc (a) a x a y d y d x t ho (a) figure 28: standard interface read cy cle timing ? asynchronous boot mode
mobile diskonchip g 3 81 data sheet, rev. 1.0 91-sr-011-05-8l table 15: standard interface read cycle timing parameters vccq=vcc vcc=2.5-3.6v vccq=1.65-2.0v vcc=2.5-3.6v symbol description min max min max units tsu(a) address to oe# setup time -2 -2 ns tho(a) oe# to address hold time 1 24 24 ns tsu(ce0) ce# to oe# setup time 2 ? ? ns tho(ce0) oe# to ce# hold time 3 ? ? ns tho(ce1) oe# or we# to ce# hold time 5 5 ns tsu(ce1) ce# to we# or oe# setup time 5 5 ns trec(oe) oe# negated to start of next cycle 20 20 ns turbo operation 87 88 read access time (ram) 1 normal operation 84 85 turbo operation 33 34 tacc read access time (all other addresses) 3 normal operation 55 56 ns oe# to d driven 4 turbo operation 5 5 ns tloz(d) oe# to d driven 4 normal operation 14 14 ns thiz(d) oe# to d hi-z delay 4 tbd tbd ns tacc(a) ram read access time from a[9:0] asynchronous boot mode 76 77 ns tho(a-d) data hold time from a[9:0] (ram) asynchronous boot mode 0 0 ns 1. add 260 ns (tbd) on the first read cycle when exiting powe r-down mode. see section 6.3 for more information. 2. ce# may be asserted any time before or after oe# is asserted. if ce# is asserted after oe#, all timing relative to when oe# was asserted will be referenced to the time ce# was asserted. 3. ce# may be negated any time before or afte r oe# is negated. if ce# is negated before oe#, all timing relative to when oe# was n egated will be referenced to the time ce# was negated. 4. no load (c l = 0 pf).
mobile diskonchip g 3 82 data sheet, rev. 1.0 91-sr-011-05-8l 11.3.2 write cycle timing standard interface ce# a[12:0] t rec (we) t ho (ce1) t su (ce0) t ho (ce0) t ho (d) t w (we) t su (d) t ho (a) t su (a) oe# d[15:0] we# t su (ce1) t wcyc figure 29: standard interface write cycle timing table 16: standard interface write cycle parameters vccq=vcc vcc=2.5-3.6v vccq=1.65-2.0v vcc=2.5-3.6v symbol description min max min max units t su (a) address to we# setup time -2 -2 ns tho(a) we# to address hold time 24 24 ns we# asserted width (ram) 38 38 ns tw(we) we# asserted width (all other addresses) 36 36 ns tsu(ce0) ce# to we# setup time 1 -- -- ns tho(ce0) we# to ce# hold time 2 -- -- ns tho(ce1) oe# or we# to ce# hold time 5 5 ns tsu(ce1) ce# to we# or oe# setup time 5 5 ns trec(we) we# to start of next cycle 20 20 ns tsu(d) d to we# setup time 27 27 ns tho(d) we# to d hold time 0 0 1. ce# may be asserted any time before or after we# is asserted. if ce# is asserted after we#, all timing relative to we# asserted should be referenced to the time ce# was asserted. 2. ce# may be negated any time before or afte r we# is negated. if ce# is negated before we#, all timing relative to we# negated wi ll be referenced to the time ce# was negated.
mobile diskonchip g 3 83 data sheet, rev. 1.0 91-sr-011-05-8l 11.3.3 read cycle timing multiplexed interface ce# ad[15:0] t rec (oe) t ho (ce1) t su (ce0) t su (ce1) t ho (ce0) t hiz (d) t acc t ho (avd) t su (avd) oe# we# avd# t w (avd) addr data t ho (avd-oe) figure 30: multiplexed inte rface read cycle timing table 17: multiplexed interface read cycle parameters vccq=vcc vcc=2.5-3.6v vccq=1.65-2.0v vcc=2.5-3.6v symbol description min max min max units tsu(avd) address to avd# setup time 5 5 ns tho(avd) address to avd# hold time 7 7 ns tw(avd) avd# low pulse width 12 12 ns t ho (avd-oe) avd# to oe# hold time 1 0 0 ns tsu(ce0) ce# to oe# setup time 1 ? ? ns tho(ce0) oe# to ce# hold time 2 ? ? ns tho(ce1) oe# or we# to ce# hold time 5 5 ns tsu(ce1) ce# to we# or oe# setup time 5 5 ns trec(oe) oe# negated to start of next cycle 20 20 ns turbo operation 87 88 read access time (ram) normal operation 84 85 turbo operation 33 34 tacc read access time (all other addresses) normal operation 55 56 ns turbo operation 5 5 tloz(d) oe# to d driven 3 normal operation 14 14 ns thiz(d) oe# to d hi-z delay 3 tbd tbd ns 1. ce# may be asserted any time before or after oe# is asserted. if ce# is asserted after oe#, all timing relative to oe# asserte d will be referenced instead to the time of ce# asserted. 2. ce# may be negated any time before or afte r oe# is negated. if ce# is negated befo re oe#, all timing relative to oe# negated w ill be referenced instead to the time of ce# negated. 3. no load (c l = 0 pf).
mobile diskonchip g 3 84 data sheet, rev. 1.0 91-sr-011-05-8l 11.3.4 write cycle timing multiplexed interface ce# t rec (we) t ho (ce1) t su (ce0) t ho (ce0) t ho (d) tw(we) t su (d) oe# we# t su (ce1) t wcyc ad[15:0] t ho (avd) t su (avd) avd# tw(avd) addr data t su (avd-we) t rec (we-avd) next addr figure 31: multiplexed inte rface write cycle timing table 18: multiplexed interface write cycle parameters vccq=vcc vcc=2.5-3.6v vccq=1.65-2.0v vcc=2.5-3.6v symbol description min max min max units tsu(avd) address to avd# setup time 5 5 ns tho(avd) address to avd# hold time 7 7 ns tw(avd) avd# low pulse width 12 12 ns tsu(avd-we) avd# to we# setup time 1 4 4 ns we# asserted width (ram) 3 38 38 tw(we) we# asserted width (all other addresses) 36 36 ns tsu(ce0) ce# to we# setup time 1 ? ? ns tho(ce0) we# to ce# hold time 2 ? ? ns tho(ce1) oe# or we# to ce# hold time 5 5 ns tsu(ce1) ce# to we# or oe# setup time 5 5 ns trec(we) we# to start of next cycle 20 20 ns tsu(d) d to we# setup time 27 27 ns tho(d) we# to d hold time 0 0 ns 1. ce# may be asserted any time before or after we# is asserted. if ce# is asserted after we#, all timing relative to we# asserted will be referenced instead to th e time of ce# asserted. 2. ce# may be negated any time before or afte r we# is negated. if ce# is negated before we#, all timing relative to we# negated wi ll be referenced instead to the time of ce# negated. 3. we# may be asserted before or after the rising edge of avd#. th e beginning of the we# asserted pulse width spec is measured fro m the later of the falling edge of we# or the rising edge of avd#.
mobile diskonchip g 3 85 data sheet, rev. 1.0 91-sr-011-05-8l 11.3.5 read cycle timing multiburst in figure 32, the multiburst control register values are: latency=0, length=4, clk_inv=0. 01 23 clk oe# d[15:0] (hold=0) 01 d[15:0] (hold=1) t p (clk-d) t loz (d) t rec (oe) t su (oe0-clk1) t hiz (d) insert latency clock cycles t(clk) t s u ( o e 0 - c l k 0 ) t ho (oe0-clk0) t ho (oe0-clk1) t w (clk0) t w (clk1) figure 32: multiburst read timing note: shown with burst mode controller register values: latency=0, length=4. table 19: multiburst read cycle parameters vccq=vcc vcc=2.5-3.6v vccq=1.65-2.0v vcc=2.5-3.6v symbol description min max min max units t su (oe0-clk1) oe# to clk setup time 1, 4 10 10 ns t su (oe0-clk0) oe# to clk setup time 1, 5 10 10 ns t ho (oe0-clk1) clk to oe# hold time 1, 4 1 1 ns t ho (oe0-clk0) clk to oe# hold time 1, 5 1 1 ns t p (clk-d) clk to d delay 24 25 ns clk high pulse width 6 7 7 ns t w (clk1) clk high pulse width 7 7 7 ns clk low pulse width 6 8 8 ns t w (clk0) clk low pulse width 7 8 8 ns clk period 6 27 27 ns t(clk) clk period 7 29 29 ns t rec (oe) oe# negated to start of next cycle 2 9 9 ns t loz (d) oe# to d driven 1,3 turbo operation 14 14 ns
mobile diskonchip g 3 86 data sheet, rev. 1.0 91-sr-011-05-8l vccq=vcc vcc=2.5-3.6v vccq=1.65-2.0v vcc=2.5-3.6v symbol description min max min max units oe# to d driven 1,3 normal operation 5 5 ns t hiz (d) oe# to d hi-z delay 1 tbd tbd ns 1. ce# may be asserted any time before or after oe# is asserted. if ce# is asserted after oe#, all timing relative to oe# asserted will be referenced instead to the time of ce# asserted. 2. ce# may be negated any time before or afte r oe# is negated. if ce# is negated before oe#, all timing relative to oe# negated wi ll be referenced instead to the time of ce# negated. 3. no load (cl = 0 pf). 4. applicable only if the clk_in v bit of the multiburst mode control register is 0. 5. applicable only if the clk_in v bit of the multiburst mode control register is 1. 6. applicable only if the hold bit of the multiburst mode control register is 0. 7. applicable only if the hold bit of the multiburst mode control register is 1 11.3.6 power supply sequence when operating mobile diskonchip g3 with se parate power supplies powering the vccq and vcc rails, it is desirable to turn both supplie s on and off simultaneousl y. providing power to one supply rail and not the other (either at powe r-on or power-off) can cause excessive power dissipation. damage to the device may result if th is condition persists for more than 500 msec. 11.3.7 power-up timing mobile diskonchip g3 is reset by assertion of the rstin# input . when this signal is negated, mobile diskonchip g3 initiates a download procedure from the flash memory into the internal programmable boot block. during this procedure, mobile diskonchip g3 does not respond to read or write accesses. host systems must therefore observe the requiremen ts described below for first access to mobile diskonchip g3. any of the following methods ma y be employed to guarantee first-access timing requirements: ? use a software loop to wait at least tp (busy1) before acce ssing the device after the reset signal is negated. ? poll the state of the busy# output. ? poll the dl_run bit of the download status re gister until it returns 0. the dl_run bit will be 0 when busy# is negated. ? use the busy# output to hold the host cpu in wait state before completing the first access which will be a ram read cycle. the data will be valid when busy# is negated. hosts that use mobile diskonchip g3 to boot the system must employ option 4 above or use another method to guarantee the required timing of the first-time access.
mobile diskonchip g 3 87 data sheet, rev. 1.0 91-sr-011-05-8l rstin # vc c busy # vcc = 2.5v vccq = 1.65 or 2.5v t p (busy1) t rec (vcc-rstin) ce#, oe # ( we# = 1 ) t p (vcc-busy0) t su (d-busy1) d (read cycle) t w (rstin) t p (busy0) avd # (muxed mode only) t su (dpd/rstin-avd) a[12:0] valid dpd (a[0]) t p (dpd/rstin-d) figure 33: reset timin g table 20: power-up timing parameters symbol description min max units t rec (vcc-rstin) vcc/vccq stable to rstin# 1 500 s t w (rstin) rstin# asserted pulse width 30 ns t p (busy0) rstin# to busy# 50 ns t p (busy1) rstin# to busy# 2 1055 s t su (d-busy1) data valid to busy# 3 0 ns t p (vcc-busy0) vcc/vccq stable to busy# 500 s t su (dpd/rstin-avd) 4,6 dpd transition or rstin# to avd# 600 ns t p (dpd/rstin-d) 5,6 dpd transition or rstin# to data valid 660 ns 1. specified from the final positive crossing of v cc above 2.7v and vccq above 1.65 or 2.5v. 2. if the assertion of rstin# occurs during a flash er ase cycle, this time could be extended by up to 500 s. 3. normal read/write cycle timing applies. this parameter applie s only when the cycle is extende d until the negation of the busy# signal. 4. applies to multiplexed interface only. 5. applies to sram mode only. 6. dpd transition refers to exiting deep power down mode by toggling dpd (a[0]). 7. when operating mobile diskonchip g3 with separate power supplies for vcc and v ccq, it is recommended to turn both supplies on and off simultaneously. providing power sepa rately (either at power-on or power-off) can cause exce ssive power dissipation. dam age to the device may result if this condition persists for more than 1 second.
mobile diskonchip g 3 88 data sheet, rev. 1.0 91-sr-011-05-8l 11.3.8 interrupt timing irq# tw(irq#) figure 34: irq# pulse width in edge mode table 21: interrupt timing symbol description min max unit tw(irq#) irq# asserted pulse width (edge mode) 250 500 nsec 11.3.9 dma request timing dmarq# t w (dmarq) note: polarity of dmarq# may be inverted based on the normal bit of dma control register[0]. oe#/ce# t ho marq-oe) t p (oe-dmarq) figure 35: dmarq# pulse width table 22: dma request timing symbol description min max unit tw(dmarq#) dmarq# asserted pulse width 250 500 nsec tho(dmarq-oe) dmarq# asserted to start of cycle 0 nsec t p (oe-dmarq) start of cycle to dmarq# negated tbd nsec
mobile diskonchip g 3 89 data sheet, rev. 1.0 91-sr-011-05-8l 11.4 mechanical dimensions 11.4.1 mobile diskonchip g3 512mb tsop-i dimensions: 20.00.25 mm x 12.00.10 mm x 1.10.10 mm figure 36: mechanical dimensions tsop-i package
mobile diskonchip g 3 90 data sheet, rev. 1.0 91-sr-011-05-8l fbga dimensions: 7.00.20 mm x 10.00.20 mm x 1.20.1 mm ball pitch: 0.8 mm figure 37: mechanical dimensions 7x10 fbga package
mobile diskonchip g 3 91 data sheet, rev. 1.0 91-sr-011-05-8l 11.4.2 mobile diskonchip g3 1gb (dual-die) fbga dimensions: 9.00.20 mm x 12.00.20 mm x 1.40.1 mm ball pitch: 0.8 mm 0.80 0.80 0.40 7.20 2.40 0.470.05 0.90 7.20 0.40 0.80 0.80 0.330.05 1.2/ 1.4 9.0 12.0 1 6 2 3 5 7 4 10 9 8 c h d e g j f m l k a b figure 38: mechanical dimensions 9x12 fbga package
mobile diskonchip g 3 92 data sheet, rev. 1.0 91-sr-011-05-8l 12. o rdering i nformation mdxxxx-dxxx-xxx-t-c device code: 4811 - diskonchip g3 tsop-i 4832 - diskonchip g3 fbga (7x10) 4331 - diskonchip g3 fbga (9x12) dual die capacity d- mbyte d- mbit xxx - value supply voltage v3q18 - 3.3v core, 1.8v i/o te mpe rature x - extended: -40 o c to +85 o c blank - commercial: 0 o c to 70 o c composition p - lead (pb) f ree blank - regular figure 39: ordering information structure refer to table 23 for combinations currently available and the associated order numbers. table 23: available combinations capacity ordering code mb mb package temperature range md4811-d512-v3q18 commercial md4811-d512-v3q18-x 48-pin tsop-i extended md4811-d512-v3q18-p pb-free commercial md4811-d512-v3q18-x-p 48-pin tsop-i pb-free extended md4832-d512-v3q18-x 85-ball fbga 7x10 extended md4832-d512-v3q18-x-p 64 512 85-ball fbga 7x10 pb-free extended md4331-d1g-v3q18-x 69-ball fbga 9x12 extended md4331-d1g-v3q18-x-p 128 1024 (1gbit) 69-ball fbga 9x12 pb-free extended md3831-d00-daisy 69-ball fbga 9x12 daisy-chain md4832-d00-daisy 00 000 85-ball fbga 7x10 daisy-chain daisy-chain format for package reliability testing md4811-d512-mech 48-pin tsop-i md4832-d512-mech 85-ball fbga 7x10 md4331-d1g-mech 00 000 69-ball fbga 9x12 mechanical sample
mobile diskonchip g 3 93 data sheet, rev. 1.0 91-sr-011-05-8l h ow to c ontact u s usa m-systems inc. 8371 central ave, suite a newark ca 94560 phone: +1-510-494-2090 fax: +1-510-494-5545 china m-systems china ltd. 25a international business commercial bldg. nanhu rd., lou hu district shenzhen, china 518001 phone: +86-755-2519-4732 fax: +86-755-2519-4729 europe m-systems ltd. 7 atir yeda st. kfar saba 44425, israel tel: +972-9-764-5000 fax: +972-3-548-8666 internet http://www.m-sys.com general information info@m-sys.com japan m-systems japan inc. asahi seimei gotanda bldg., 3f 5-25-16 higashi-gotanda shinagawa-ku tokyo, 141-0022 phone: +81-3-5423-8101 fax: +81-3-5423-8102 taiwan m-systems asia ltd. room b, 13 f, no. 133 sec. 3 min sheng east road taipei, taiwan r.o.c. tel: +886-2-8770-6226 fax: +886-2-8770-6295 sales and technical information techsupport@m-sys.com ? 2003 m-systems flash disk pioneers, ltd. all rights reserved. this document is for information use only and is subject to cha nge without prior notice. m-systems flash disk pioneers ltd. ass umes no responsibility for any errors that may appear in this document. no part of this document may be reproduced, transmitted, transc ribed, stored in a retrievable manner or translated into any language or computer la nguage, in any form or by any means, electronic, mechanical, m agnetic, optical, chemical, manual or otherwise, w ithout prior written consent of m-systems. m-systems products are not warranted to ope rate without failure. accordingly, in a ny use of the product in life support systems or other applications where failure could cause inju ry or loss of life, the product should only be incorporated in systems designed with appropriate and sufficient redundancy or backup features. contact your local m-systems sales office or distributor, or visit our website at www.m-sys.com to obtain the latest specificat ions before placing your order. m-systems? is a registered trademark. di skonchip?, diskonchip millennium?, diskonkey?, smart diskonkey? and trueffs? are registered trademarks of m-systems. diskonkey mykey?, ff d?, fly-by?, idiskonchip?, idoc?, mdiskonchip?, mdoc?, mobile diskonchip?, supermap?, udiskonchip? and udoc? are tr ademarks of m-systems. other product names mentioned in this document may be trademarks or registered trademarks of their respective owners and are hereby acknowledged.

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